Abstract: A method for dynamic scheduling of data transmission for a large number of data channels under the available bit rate (ABR) service protocols of asynchronous transfer mode (ATM) uses a schedule table and ready queue. In this method, at each time slot, data channels referenced in the current entry of the schedule table is removed from the schedule table and appended to the ready queue. At each available transmission time slot, an ATM cell is transmitted from the data channel referenced in the record at the head of the ready queue. The data channel is then rescheduled for in the schedule table for the next transmission. The present invention also accommodates data transmission rates related to fractional time slot intervals.

Abstract: A semiconductor package includes a semiconductor die, a lead frame and die attach paddle, and a thermally conductive metal foam porous sponge attached to the die attach paddle to conduct heat generated by operation of the die to the outside of the semiconductor package. In another embodiment the chip is mounted directly on the sponge. A flip-chip interconnection is also disclosed. In the method, a die and lead frame assembly is placed on a sponge in the cavity of a package two-part mold, the mold is closed and filled with encapsulant. A ball grid array semiconductor package with an internal sponge heatsink mounted directly on or in a substrate such as a printed circuit board with circuitry metallization, and a semiconductor die, wire-bonded or soldered to the metallization and adhered to the sponge heatsink, is also included.

Abstract: An apparatus and method for improving the execution speed of macro instructions which have an operand located in memory, and where the destination of the result is in memory. The apparatus includes an ALU Store which monitors micro instructions generated by a translator. When a macro instruction is fetched which has an operand located in memory, and the result is to be stored in the same location in memory, the translator generates a LOAD micro instruction followed immediately by an operation micro instruction which contains STORE indicia, such as a STORE suffix. The ALU Store latches the address created by the LOAD micro instruction, and uses this latched address in the following operation store micro instruction.

Abstract: Tri-port memory buffers having fast fall-through capability contain a custom tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. In particular, a preferred tri-port memory array is provided having a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports.

Abstract: In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when the other ports are reading previously-stored data of opposite polarity. A parallel write capability is disclosed which eliminates such row contention by using the other ports of a multi-port memory to assist in writing the memory cell. By forcing the other ports into a write of the same data there can be no contention. Whenever a read port accesses the same row as a write port, the read port's bitline corresponding to the selected column for the write port is also forced into a write of the write port's data, along with the write port's bitline corresponding to the selected column of the write port. The read port's data is unaffected regardless of whether the selected column for the read port differs from the selected column for the write port.

Abstract: A method for forming trench isolation with spacers on the corners where the silicon and oxide intercept. A cavity is formed in silicon with a mask. Prior to completely removing the mask, the mask is further etched to enlarge the upper portion of the cavity. The cavity is filled with oxide, which is subsequently etched to produce a dome-shaped cap, protective of sharp silicon corners that would otherwise upset electrical characteristics of transistors.

Abstract: Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data.

Abstract: An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. The error locator polynomial calculator includes an R-Q calculator, a .lambda.-.mu. calculator, an R-Q degree calculator and a trigger circuit. These calculators and the trigger circuit can be implemented each as a plurality of generic cells. The number of generic cells can be changed to construct Reed-Solomon circuits for different Reed-Solomon codes. The R-Q, .lambda.-.mu. and R-Q degree calculators provide adaptive circuits that use switches and multiplexors, for example, to adapt to perform appropriate calculations based upon the nature of the error correction polynomials applied to the inputs of the calculators. The R-Q, .lambda.-.mu.

Abstract: A method for preprocessing a binary file for data compression under a dictionary-based data compression algorithm takes advantage of redundancy in a two-dimensional binary image. The method rearranges a linear representation of a binary image, i.e. a representation based on pixels of horizontal lines, to a two-dimensional representation, i.e. a representation based on a sequence of adjoining picture areas, to achieve an improvement of compression ratio. The present invention is applicable to dictionary-based data compression methods, such as LZW, LZ77 and LZ78.

Abstract: A method and apparatus for testing integrated circuit devices includes a dual site loadboard (60) with dual test sites (62) for holding integrated circuit devices. The dual test sites are connected to test instruments. Integrated circuit devices are loaded onto the dual test sites and tested one at a time using the same set of pin cards (34) in a test head (30).

Abstract: An input buffer includes an n-channel FET having a drain region coupled to the V.sub.cc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: An improved flip-chip bond connection and bonding method uses a "press fit" bond between a set of bond pad bumps or projections on a semiconductor chip and corresponding set of substrate bumps or projections on a substrate to self-align the chip with the substrate and enable flip-chips to be inexpensively bonded to substrates or packages with greater accuracy and a smaller pad pitch than previously achieved. In the method after normally one of the sets of bond pad bumps or substrate bumps has been cooled to shrink or contract so that the facing surfaces of each of the pad bumps and substrate bumps can be interdigitated, the chip and substrate are moved together so that the respective bumps are in a substantially common plane. The one cooled set of bumps is then warmed to expand that set of bumps sufficiently to form a lateral press-fit force between the facing surfaces, physically securing and electrically connecting the respective sets of bumps.

Abstract: Apertures in a tape formed on a substrate allow straight plating of solder bumps to heights above 4 mils. The solder bumps are combined with a lower density material to form an hourglass-shaped structure which allows interconnections to bonding pads of electronic components with pitches less than 9 mils.

Abstract: A method and structure for a surface mountable rigid-flex printed circuit board is disclosed. A rigid-flex circuit board is mounted onto a printed circuit board using standard surface mount technology such as ball grid array, pin grid array or solder screen print.The use of rigid-flex board allows tested, burned in components to be used while still allowing a small multiple chip module footprint.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: An apparatus and method for loading a pointer into a selector register/general purpose register pair is provided. The apparatus and method utilizes a single micro instruction to load an offset directly into the general purpose register, during the write back stage of a pipeline, while storing the old value in the general purpose register into a temporary register, in an earlier stage in the pipeline. Thus, the general purpose register is overwritten with the offset before the selector load completes. If the selector load operation fails, the general purpose register may be restored from the temporary register.

Abstract: Methods, systems and computer program products for texturing a picture element of an image. These methods, systems and computer program products include blending texture values from a first texture map corresponding to a first level of detail with texture values from a second texture map corresponding to a second level of detail to create a textured value for the picture element. The blending of the two texture maps, however, only occurs if the magnitude of deviation of the level of detail corresponding to the picture element from a level of detail of the first texture map is greater than a threshold value. The threshold value may be selected based upon the perceptibility of differences between the level of detail of the picture element and the level of detail of the first texture map.

Abstract: In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current.

Abstract: The pulldown transistors of an SRAM cell are made to have higher threshold voltages and thinner gate insulating layers than the access transistors of the cell. In some embodiments, this allows a reduced supply voltage Vcc (for example, 3.3 volts) to be used in a reduced geometry (for example, 0.30-0.35 micron gate length) SRAM cell without reducing cell ratio, compromising cell stability, incurring oxide degradation from hot carrier injection or causing punch through problems. A mask is used to remove a first gate insulating layer from the pulldown transistor area and not from the access transistor area. In some embodiments, this same mask is then used to increase the threshold voltages of the pulldown transistors and not the access transistors by masking the access transistor areas from a shallow implant that increases transistor threshold voltage. After removing the mask, a second gate insulating layer is formed in both the pulldown and access transistor areas.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator includes a thermoelectric cooler used to electrically control the board simulator's thermal resistivity. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.