Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data is storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: Integrated circuit output buffers include first and second pull-down switches and a preferred pull-down control circuit which utilizes a preferred feedback technique to facilitate a reduction in simultaneous-switching noise during pull-down operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback technique also limits the degree to which external noise can influence operation of the pull-down control circuit. First and second pull-up switches and a pull-up control circuit are also provided to improve simultaneous-switching noise and impedance matching characteristics during pull-up operations in a similar manner. The first and second pulldown switches are electrically connected in parallel between an output of the buffer and a first reference signal line (e.g., Vss) and the first and second pull-up switches are electrically connected in parallel between an output of the buffer and a second reference signal line (e.g., Vdd).

Abstract: A heat sink mounted on an electronic component causes a thermal plume effect so that air adjacent to the electronic component moves through one or more channels in the heat sink in a direction substantially transverse to and away from the electronic component. The heat sink includes a base attachable to the electronic component, a support member mounted on and substantially transverse to the base, and a heat exchanger mounted on the support member and spaced away from the base. The heat exchanger has at least one entry hole adjacent to the base, at least one exit hole at a distance from the entry hole, and one or more channels adjacent to the support member and in flow communication with the entry hole and the exit hole.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: Semiconductor devices are formed in a semiconductor substrate having an essentially planar upper surface. In some embodiments, implanted regions are formed in the substrate at a first predetermined depth by implantation of oxygen and/or nitrogen ions. In some embodiments buried implanted are formed in the substrate at a second predetermined depth, deeper than the first depth by implantation of oxygen and/or nitrogen ions. These implanted regions are converted to dielectric isolation regions and buried dielectric regions, respectively, by a high temperature anneal after formation of a gate structure.

Abstract: A circuit for protecting the internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge events is presented. The circuit comprises a trigger circuit including a resistor and diode array coupled between a power line and a ground line and a discharge circuit which, when turned on by an output signal of the trigger circuit, conducts the excess charge on the power line to ground.

Abstract: A method and apparatus for equalizing a received quadrature amplitude modulated signal is disclosed. To equalize the signal, a band edge equalizer (BEE) is used in combination with a symbol spaced equalizer (SSE) and possibly a decision feedback equalizer (DFE). The equalizer's are used along a series path to equalize the QAM signal in a series of equalization operations. By separating the equalization of the signal to separate equalizers, the cost of the equalization can be reduced without substantially affecting performance. In particular, band edge equalizing the QAM signal and symbol space equalizing the symbol can reduce the number of multiplies per second required by any particular equalizer. Accordingly, the equalizers used can be less expensive. Also, using a decimating circuit between the BEE and the SSE that decimates the sample rate of the signal being provided to the SSE can further reduce the number of multiplies per second that must be performed by the SSE.

Abstract: A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.

Abstract: A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the substrate, the polysilicon layer having a raised first portion overlying the gate structure. A masking layer is formed overlying the polysilicon layer and then blanket etched to expose the raised first portion of the polysilicon layer which is subsequently removed. Since the raised first portion of the polysilicon layer is removed without using photolithography, high density MOSFETs are readily fabricated.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator includes a thermoelectric cooler used to electrically control the board simulator's thermal resistivity. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.

Abstract: A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.

Abstract: A 6-T SRAM cell having a MOS transistor with source/drain regions having an absence of heavily doped portions characteristic of prior art lightly doped drain (LDD) MOS devices is fabricated. Forming the MOS transistor with an absence of heavily doped portions of source/drain regions allows the width of the MOS gate layer, the width of the MOS source/drain regions and the width of the field oxide region between active regions of the SRAM cell to be reduced compared to the prior art. Accordingly, the present SRAM cell occupies less chip area than a prior art SRAM cell. Further, forming the MOS transistor without heavily doped portions of source/drain regions improves latch-up immunity and decreases write cycle time of the present SRAM cell.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.

Abstract: Tri-port memory buffers having fast fall-through capability contain a custom tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. In particular, a preferred tri-port memory array is provided having a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports.

Abstract: A compensation circuit which accounts for variations in both temperature and V.sub.CC supply voltage on an integrated circuit. The compensation circuit includes four quasi-independent compensation current sources, each of which generates a corresponding compensation current. The first compensation current source generates a first compensation current which has a positive slope with respect to temperature. The second compensation current source generates a second compensation current which has a negative slope with respect to temperature. The third compensation current source generates a third compensation current which has a negative slope with respect to the V.sub.CC supply voltage. The fourth compensation current source generates a fourth compensation current which has a positive slope with respect to the V.sub.CC supply voltage. The first, second, third and fourth compensation currents are summed to create a total compensation current.

Abstract: A structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the semiconductor substrate, a conductive interconnect layer having a plurality of conductive traces located over the first insulating layer, and a patterned insulating layer located over the patterned interconnect layer. One or more trenches are formed in the upper surface of the first insulating layer. These trenches, which do not extend completely through the first insulating layer, are located between adjacent traces of the interconnect layer. A dielectric material having a low dielectric constant is located in these trenches, and between adjacent traces of the patterned interconnect layer. The trenches advantageously maximize the volume of low dielectric constant material which is located between the traces.

Abstract: An insulating layer having an irregular upper surface is provided to improve the adhesion and increase the coefficient of friction between the insulating layer and a bonding pad formed over the insulating layer. By making the upper surface of the insulating layer irregular, the area of contact between the bonding pad and the insulating layer is increased. As a result, the adhesion between the bonding pad and the insulating layer is also increased. This prevents the bonding pad from being detached from the insulating layer when a bonding wire is later attached to the bonding pad. The upper surface of the insulating layer can be made irregular by etching one or more cavities in the upper surface of the insulating layer. The upper surface of the insulating layer can alternatively be made irregular by forming one or more raised structures beneath the insulating layer. The raised structures cause plateaus to be formed at the upper surface of the insulating layer.