Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

Abstract: The invention relates to a method for detecting video frame types with median filtering, which proceeds a denoising step after calculating the comb factor of each pixel, to avoid incorrect judgment of the frame type resulting from excessive field difference and improve detection accuracy.

Abstract: A residual frequency offset (RFO) compensation method and a compensation system of a multi-carrier communication system is disclosed. The compensatory method of present invention includes two phase-computation steps. The first phase-computation step processes a phase variation of an OFDM data symbol each time to obtain a RFO estimation for compensating a demodulation carrier. The second-phase computation processes a plurality of OFDM data symbols each time to obtain a RFO estimation for compensating the demodulation carrier.

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: Non-multiple delay element values that may be implemented to reduce periodic quantization errors associated with phase shifting devices used in phased array apparatus. The non-multiple delay element values may be implemented so that a magnitude of phase shift imparted by a given delay element of a phase shifting scheme is not a multiple or a factor of the magnitude of the phase shift imparted by any other delay element employed in the same phase shifting scheme.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.

Abstract: An interpolation circuit (10) generates a plurality of intermediate amplitude values linearly related to two consecutive signal amplitude values using a system of adders and memory elements. A first stage (64) of the interpolation circuit calculates a one-half amplitude value; a second stage (66) calculates one-fourth and three-fourths amplitude values, and a third stage (68) calculates one-eighth, three-eighths, five-eighths, and seven-eighths amplitude values. A comparator (14) receives a threshold value (32) and compares each of the intermediate amplitude values to the threshold value. A decoder (16) generates a time of arrival adjustment value that is subtracted from a low resolution time of arrival to generate a high resolution time of arrival.

Abstract: The present invention discloses a gain amplifier, capable of concurrently operating at three different frequency bands. The gain amplifier comprises an amplification stage for amplifying a signal applied to an input of the amplifier and a triple-band resonance load connected between a DC bias voltage and a DC bias input of the amplification stage. The triple-band resonance load uses a set of reactive elements to provide match in a first frequency band, a second frequency band and in a third frequency band, such as at 2.4 GHz, 5.8 GHz and 9.0 GHz. According to the gain amplifier of the present invention, it can effectively provide triple-band signal amplification and in-band interference suppression for various multi-standard coexist communication systems.

Abstract: A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads, and the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads that does not electrically connect to anyone of the first pads electrically connects to the interconnection-wiring layer. In another case, a shielding portion, which electrically connects the interconnection-wiring layer, is provided around the second pad that doesn't electrically connect to anyone of the first pads. Furthermore, this invention also discloses a semiconductor device including the substrate.

Abstract: A rate control method with region of interesting support, which coding macroblocks in a current picture with different priority. The rate control method calculates a weighted macroblock activity according to the priority and a macroblock activity and a picture activity for the current picture according to the weighted macroblock activity. Then, the method allocates a bit budget for each macroblock according to the priority and calculates an estimated complexity for the current picture according to a complexity of a previously coded picture, an activity of the previously coded picture and the weighted macroblock activity. The method also calculates an estimated quantizer scale according to the estimated complexity and the bit budget, an initial virtual buffer occupancy according to an reaction factor and the estimated quantizer scale and a macroblock quantizer scale according to a virtual buffer occupancy of a previously coded macroblock, the priority and the reaction factor.

Abstract: The method and apparatus use two inequalities to determine whether an estimated value obtained from conventional method and a correct value obtained from ideal conversion is identical. When those values are the same, the estimated value is not corrected; otherwise, according to the difference between those values, one is added or subtracted from the estimated value to obtain the correct result.

Abstract: An interconnection device includes a carrier housing formed of non-conductive material and has at least one cavity extending through the housing. Within the cavity is disposed a non-formed compression contact that has a cantilevered beam portion that is tapered along its length. The may be tapered such that that deflection of the beam occurs across substantially the entire length of the beam when a compression force is applied to the contact. The contact may be installed in the housing such that it has some freedom of movement in the x, y, and z directions.

Abstract: A method for PCI Express Power Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex. The method includes converting a Beacon signal generated by the PCI Express Root Complex into a Pseudo-PME signal, the Beacon signal asserting the Pseudo-PME signal. A Pseudo-PME line electrically connected with an PME input of the PCI PME controller and the PCI Express Root Complex is provided for transmitting the Pseudo-PME signal to the PCI PME controller. The PME input receives PME signals generated by PCI-compliant devices through a PCI Bus of the computer system. Before the computer system is under the control of an operating system, the Pseudo-PME signal is de-asserted.

Abstract: An apparatus and a method of controlling clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of phase intervals therebetween. A predetermined phase angle is divided by the number of the output signals to generate one of the phase intervals. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signal and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signal.

Abstract: A method for PCI ExpressPower Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex. The method includes converting a plurality of PM_PME packets generated by the PCI Express Root Complex into a Pseudo-PME signal, a first PM_PME packet of the plurality of PM_PME packets asserting the Pseudo-PME signal. A Pseudo-PME line electrically connected with a PME input of the PCI PME controller and the PCI Express Root Complex is provided for transmitting the Pseudo-PME signal to the PCI PME controller. The PME input receives PME signals generated by PCI-compliant devices through a PCI Bus of the computer system. The method further includes de-asserting the Pseudo-PME signal. The de-assertion of the Pseudo-PME signal follows the assertion of the Pseudo-PME signal by a predetermined time interval.

Abstract: A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

Abstract: Vehicular traffic data is obtained using a traffic sensor having an antenna/transceiver module, a DSP and a microcomputer. This involves (a) transmitting radiation at a vehicles on a roadway; (b) receiving the radiation reflected back from the vehicles; (c) producing a stream of electrical signals based on the radiation reflected back from the vehicles; (d) processing the stream of electrical signals using the DSP to determine if a vehicle detection threshold is met, and, if the vehicle detection threshold is met, to determine an initial vehicle position; (e) when the vehicle detection threshold is met, generating a first signal representing the initial vehicle position using the DSP; (f) transmitting the first signal to the microcomputer; (g) deriving a first traffic information signal from the first signal using the microcomputer; (h) transmitting the first traffic information signal to an external traffic management system.

Abstract: A differential amplifier having a positive input terminal, a negative input terminal, an output terminal, a bias terminal and a ground terminal is provided. The differential amplifier comprises a differential pair circuit and a current mirror circuit. Wherein, the differential pair circuit is coupled to the positive input terminal, the negative input terminal, the output terminal, and the bias terminal of the differential amplifier. The current mirror circuit receives a constant current from a current source, and mirrors the constant current to the differential pair circuit. The current mirror circuit further connects to the ground terminal of the differential amplifier, and the terminal of the current mirror circuit receiving the constant current is coupled to a first source/drain terminal of a first PMOS transistor. A second source/drain and a gate of the first PMOS transistor are connected to the bias terminal and the output terminal of the differential amplifier, respectively.

Abstract: An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.