Abstract: The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.
Abstract: A carrier recovery apparatus for digital Quadrature Amplitude Modulation (QAM) receivers is disclosed. The carrier recovery apparatus includes a phase detector, a lock controller, a frequency locker and a phase loop filter, and provide phase/frequency error information for a numerically controlled oscillator (NCO) to generate recovered carrier frequency. The phase detector detects the symbol energy information and the phase error information of the extracted symbols from the I/Q extractor. The lock controller monitors the symbol energy from the phase detector, separates the extracted symbols into two groups: valid and non-valid, and outputs the control flag of valid symbols into both the frequency locker and the phase loop filter. To achieve a wide range acquisition and a good tracking performance, the lock controller controls the operation of the frequency locker and the phase loop filter in three operations.
Abstract: A method for motion pixel detection with a static counter map so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process, respectively.
Abstract: A covering assembly for covering an open container of a vehicle is characterized by the provision that the electric circuit controlling the movement of the cover is automatically opened when the cover reaches either the fully covered position or the fully uncovered position. The assembly includes a flexible cover attached at one end of the container body by a cover spool for retraction and extension the cover over the open container body. The cover spool is spring biased tending to uncover the open container. A bail assembly is pivotally mounted with a cover support section connected to the second end of the cover and is spring biased so as to extend the cover over the open container. A motor assembly rotates the spool and is controlled by an electric circuit that is automatically opened when the cover reaches either the fully covered position or the fully uncovered position.
Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.
Abstract: A distributed video stream decoding system on computer and decoding method of the system is proposed to increase the decoding efficiency. The decoding method reads pictures of video stream and divides each picture into a plurality of slice packages through software modules executing on a CPU. Then, the method dispatches the slice packages by slice dispatcher and sends at least a slice into a master decoder when the slice queue of the master decoder less then a default value and sends a slice into a secondary decoder when the secondary decoder is waiting, respectively. Therefore, the master decoder and the secondary decoder can decode the received slice simultaneously to increase the decoding efficiency.
Abstract: An low-voltage triggered PNP device for input signals with voltage level larger than VDD or less than VSS. The ESD protection device provides an ESD path from a first to a second node for protection of an internal circuit. The device comprises a substrate of a first conductivity type coupled to the first node, a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated, a second doped region of the first conductivity type in the first doped region coupled to the second node, and a third doped region in the substrate, adjacent to the first doped region, to have a low trigger voltage.
Abstract: An apparatus for generating and providing a stable reference voltage to a boost regulator. The apparatus comprises a clamping circuit that is configured to receive a constant voltage and a variable voltage. The clamping circuit is further configured to generate the reference voltage based on the constant voltage and variable voltage. The clamping circuit provides the reference voltage to the boost regulator at a level that is at least sufficient to cause the boost regulator to output a non-zero voltage.
Abstract: A method and apparatus for adapting and applying current boost levels to precharge current-driven elements in a matrix, and a method to make devices for this purpose. Elements are driven during successive scan cycles, each having a precharge period and an exposure period. One or more conduction voltages are sensed while an element conducts a selected exposure current, with early samples taken nearer the beginning of exposures and late samples taken nearer the end. Charge delivered during the precharge period is adjusted to reduce differences between early and late voltage samples.
Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.
Abstract: The present invention discloses a filter using multilayer ceramic technology. The filter comprises an input port, an output port, a first lumped resonator and a first step-impedance resonator connected to the input port, a second lumped resonator and a second step-impedance resonator connected to the output port, a coupling capacitor used for the coupling of the first lumped resonator and the first step-impedance resonator to the second lumped resonator and the second step-impedance resonator. The filter according to the present invention can provide the multi-transmission zeros in the stopband to isolate the adjacent channel and suppress the harmonics, and provide the transmission poles in the passband to have lower insertion loss. In addition, a manufacturing method for the filter using multilayer ceramic technology is also disclosed.
Abstract: An optical detection system for forming an image of a field of view in an object plane onto an image plane in which the electromagnetic radiation image is transmitted to a detector array at the image plane via an optical distorting element such as a reflector 11, so as to impose a non linear relationship between areas in the image and object planes.
Type:
Grant
Filed:
December 21, 2001
Date of Patent:
March 7, 2006
Assignee:
Infrared Integrated Systems Limited
Inventors:
Stephen George Porter, John Lindsay Galloway
Abstract: An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.
Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
Abstract: A method and system for controlling a voltage used for precharging current-driven elements in a matrix, and a method of manufacturing a device to perform this function. Elements are driven during successive scan cycles, each having a precharge period and an exposure period. The elements conduct current during conduction periods, which typically have variable length within exposure periods. Conduction voltages are sensed at earlier times (e.g., near the beginning) and later times (e.g., near the end) within conduction periods. A precharge voltage is adapted based on a comparison of the earlier and later sensed conduction voltages, typically so as to reduce any average difference and thereby cause the voltage during exposure to be consistent.
Abstract: A method for detecting dynamic video pixels by using adaptive counter threshold values according to field difference value of the frame in the video, thereby to determine whether the frame is an interlaced frame or a progressive frame and to eliminate incorrect judgements resulting from field difference and to improve accuracy of frame determination.
Abstract: A method of testing resistance bolometer arrays involves applying different voltages to different bolometers so as to produce a detectable difference between adjacent bolometers under normal conditions. The voltages may be applied in a recognizable pattern so that faults can be readily identified from a visual display of the array.
Type:
Grant
Filed:
March 14, 2002
Date of Patent:
January 31, 2006
Assignee:
Infrared Integrated Systems Limited
Inventors:
Stephen George Porter, John Fox, Bhajan Singh
Abstract: A method of identifying the presence of turbulence in fluids, e.g. for distinguishing flames from other hot bodies, examines the correlation between adjacent pixels of an array viewing the fluid and particularly the proportion of negative correlation in the presence of strong positive correlation.
Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.
Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (?1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2?K)+(Bx·2?N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1?Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N?K) bits of fx, 0?K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.