Abstract: A load board for packaged IC testing. The load board with predetermined testing circuit thereon has bonding pad areas on its surface. A plurality of bonding pads is formed on the bonding pad areas, each of which is disposed corresponding to a lead of a packaged IC for testing connection, such as a quad flat packaged IC (QFP), a dual inline packaged IC (DIP) or a small outline packaged IC (SOP). The bonding pads on the load board connect the leads of the testing IC directly during IC testing, thus the conventional test socket between a conventional load board and a packaged IC is omitted.

Abstract: Systems and methods for analog to digital conversion that may be implemented using a digital to analog converter (DAC) to provide negative feedback to at least Partially cancel one or more signals (e.g., one or more interfering signals present with one or more desired signals, one or more strong desired signals, etc.) at the analog input of an analog to digital converter (ADC), and that may be used to extend the effective dynamic range of an ADC. The effective dynamic range of an ADC may be extended by detecting and isolating signals and using digital adaptive digital filtering along with a digital to analog converter (DAC) to provide negative feedback to cancel the signal/s at the input of the ADC.

Abstract: A method for scaling a digital picture to generate a scaled picture including following steps:(a) scaling a portion of the digital picture instead of the whole digital picture in a first direction; (b) scaling part of the data produced in step (a) in a second direction; and (c) repeating steps (a) and (b) to form the scaled picture.

Abstract: The invention provides a method and an apparatus for dithering, and inversely dithering an image. The apparatus makes use of a pixel address and a pixel data to locate a dither reference value from a dither matrix and use the dither reference value to convert an original pixel data having N bits into a dithered pixel data having M bits (N>M). On the other hand, the apparatus for performing an inversely dithering process makes use of the pixel address and the dithered pixel data (M bits) to locate a dither reference value from a dither matrix. Then, the dither reference value is employed to perform an inversely dithering process to recover the dithered pixel data into original pixel data.

Abstract: An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.

Abstract: A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks.

Abstract: An apparatus to determine and apply a voltage to precharge current-driven elements in a matrix. During ordinary scan cycles, a conduction voltage is sensed while the elements conduct a selected current. While not conducting the selected current, the sensed conduction voltage is averaged with other conduction voltages, and based on the averaged voltage a precharge voltage is provided during a precharge period of the scan cycle.

Abstract: A method to determine and apply a voltage to precharge current-driven elements in a matrix. During ordinary scan cycles, a conduction voltage is sensed while the elements conduct a selected current. While not conducting the selected current, the sensed conduction voltage is averaged with other conduction voltages, and based on the averaged voltage a precharge voltage is provided during a precharge period of the scan cycle.

Abstract: A write protection mechanism may be implemented that is external to a non-volatile memory device and/or that is external to controller/s that interface with the non-volatile memory device, thus providing increased security over unauthorized and/or undesirable write cycles to the memory device. Write protection security may be further enhanced by providing a write protection control signal that is external to the non-volatile memory and attached memory controller/s, thus preventing accidental or intentional override.

Abstract: A system for providing balanced currents at locations in devices requiring accurate, matched and repeatable current sources, for example visual displays having arrays of light-emitting sources. In one embodiment, the system provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The system allows for more closely matching currents at adjacent columns in a device such as a visual display, wherein the currents are driven by separate driver circuits, thereby eliminating discontinuity in brightness across the entire display area and providing higher quality visual display devices. Another embodiment provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The system additionally allows for balancing currents at adjacent columns or regions throughout the device.

Abstract: An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.

Abstract: A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.

Abstract: A method for a 3:2 pull-down film source detection. First, a source is received. Then, field differences of two fields of the same type in the source and an average field difference according to the field difference corresponding to at least one prior field in the source are calculated. The source is established as a 3:2 pull-down film source by checking whether a 3:2 pull-down signature is in the source according to the field difference and the average field difference, and a bad editing point is detected according to an interlaced frame information of the source.

Abstract: A method of predicting current boost levels and applying them to precharge current-driven elements in a matrix, and a method of manufacturing devices for this purpose. Elements are driven during successive scan cycles, each having a precharge period and an exposure period. One or more conduction voltages are sensed while an element conducts a selected current, either during a calibration cycle or during an exposure. A correct boost current is predicted from the conduction voltage(s) based upon other parameters including column capacitance, which may be determined upon manufacture, and the predicted boost current is then applied to matrix elements.

Abstract: A method for a 3:2 pull-down film source detection. First, a source is received. Then, field differences of two fields of the same type in the source and an average field difference according to the field difference corresponding to at least one prior field in the source are calculated. The source is established as a 3:2 pull-down film source by checking whether a 3:2 pull-down signature is in the source according to the field difference and the average field difference, and a bad editing point is detected according to an interlaced frame information of the source.

Abstract: A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

Abstract: An equalization method and device for equalizing the received vestigial sideband (VSB) signal, utilizes segment-sync symbols, Sato directions, erasure slicers, and variable step-sizes. In addition to stop-and-go (SAG) mode, the directions of Sato errors can also be used for speed up the convergence of tap weights of the equalizer. Erasure slicers can mitigate the effect of decision errors as they are passed through the feedback filter. In time-variant environments, variable step-sizes help the equalizer tracking the variations of the channels; in time-invariant environments, variable step-sizes help ease the fluctuations of the steady-state equalizer tap weights, and therefore yield smaller mean-squared-error and better symbol error rate (SER).

Abstract: A system for butt welding expansion joint rails with an electroslag welding system. The electroslag welding system for butt welding the expansion joint rails comprises a control system. The method for butt welding the two expansion joint rails with the electroslag welding system comprises defining a weld cavity with a first expansion joint rail, a second expansion joint rail, a plurality of gland shoes, and a pair of butt shoes. The electroslag welding system can also be adapted to weld a expansion joint rail to a support beam. The method for welding the expansion joint rail to the support beam comprising placing the expansion joint rail on a horizontal axis, placing the support beam on a vertical axis and clamping a modular component system to the expansion joint rail.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.