Abstract: Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

Abstract: A circuit which differentially amplifies voltages that are close to ground with differences of about 0.15 volts uses voltage level shifters, a cross coupled current source and inverters to provide increased speed, accuracy, and gain. Symmetric cross coupled current sources are used in a differential amplifier to provide the differential amplifier with a balanced load. A symmetric and balanced layout senses smaller voltage differences and operates faster than would otherwise be possible. The gain of the cross coupled current source is controlled by four FETs. Voltage level shifters at the input to the differential amplifier allow the differential amplifier to sense signals that are close to ground with a voltage difference of about 0.15 volts. The voltage level shifters also shift the signals to a voltage that increases the gain of the differential amplifier. Two inverters block half level signals from being outputted until the sense amplifier data has been latched.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

Abstract: A telephone communication system for communicating between a plurality of exterior telephone lines and a single common in-house two wire line is comprised of a control unit for coupling to the plurality of exterior telephone lines and for controlling communication between the plurality of telephone lines and the common two wire line. A plurality of station units are coupled remotely throughout the building to the common two wire line. The control unit communicates on the digital channel with the plurality of station units in a time frame subdivided into a plurality of time slots. A specified portion of each time slot is reserved for control communication between the control unit and each one of the plurality of station units. A synchronization signal is transmitted for phase locking all the station units to the control unit clock and a common frame synchronization signal is used to align all units in time.

Abstract: The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are all precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase.Next during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase.In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.

Abstract: In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The cascaded differential amplifiers have trigger points set by varying the channel widths of the input FETs to the CMOS differential amplifiers, or by adjusting the gains of the CMOS differential amplifiers to match the trigger point of the CMOS inverter coupled to its output. The trigger circuit is powered down to zero power dissipation whenever it is inactive.

Abstract: A load balancing arm is shown and described as having improved control including a programmable control element and electronic air regulation to provide precise and controllable lifting force on a load. The disclosed load balancing arm responds to slight operator applied force to aid in movement of the load in overcoming system hysteresis, friction and load inertia without requiring the operator to apply a sufficiently large magnitude force to overcome such counteracting forces in the system. The disclosed load balancing arm further includes automatic load weight detection sensors for accommodating variation in load weights while applying a lifting force to the load which substantially equals the weight of the load. This allows the operator to move the load freely throughout a work space.

Abstract: The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential sense output. Leakage currents and voltages common to both the dummy bit lines and selected bit line are thus cancelled out.Sense amplifiers incorporating this advantage may also be used in combination with a dynamic latch which is selectively disconnected from the memory array at all times other than during a memory cycle to avoid noise interference.Dummy word lines used in combination with dummy predecoder and decoder are used to make on-chip determinations of the transition points when an address signal is valid and complete. The actual initiation of the addressing of the memory may then be triggered according to a modeled transition point within each memory circuit.

Abstract: A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

Abstract: The performance of a Very Large Scale Integrated Read-Only Memory Circuit is improved by providing an architecture for columns of memory cells so that a signal from an addressed memory cell need propagate on diffusion bit lines by a distance approximately equal to the length of the diffusion bit line within a single block of memory cells. The architecture of the memory layout is improved by providing bit line and virtual ground line contacts at opposing ends of the memory block and by replicating the memory block through mirror symmetry on the semiconductor substrate. The memory array is further improved by providing bank selection transistors for each bank at each opposing end of a memory block so the propagation signal of an addressed memory cell need only travel the length of a single bit diffusion line in the bank.

Abstract: A video display system is provided which compensates for video processing delays in multiple, inter-coupled video processing subsystems. The video display system is comprised of multiple video processing subsystems, each having a video bus for coupling video data between individual ones of the multiple subsystems. Each subsystem is adapted to receive one or more video data inputs and to selectively and programmably process the one or more video data inputs to provide a video data output. Each subsystem is comprised of a video delay subsystem coupled to an external video source and to the video bus. The video delay subsystem adds a programmable time delay to its respective external video source input data prior to coupling it to its respective processor for processing of video data contained within that respective video processing subsystem.

Abstract: Programmable apparatus for digital processing of video signals from multiple sources converted to digital format to provide real-time multiple simultaneous special video effects and suitable for direct interface to a conventional microcomputer bus such as an Apple Macintosh II NuBus. The apparatus includes a matrix of multipliers to do real-time video processing permitting special effects such as fading between at least two video image sources, as well as a priority resolver to control display on a pixel by pixel basis of more than ten sources based upon dynamically programmable priority. In addition, a programmable multiple range thresholder, a hardware window generator capable of generating multiple simultaneous windows, a color look up table and optional image capture capabilities are provided. The apparatus also provides for a light pen input, genlocking and a range of special video effects including zooming, mosaicing, panning and blending.

Abstract: A parallel plate reactor having a grounded grid disposed between an RF powered electrode and a grounded electrode upon which a substrate is disposed. A method of utilizing the above apparatus consists of etching the substrate using a composition of 30-100% NF.sub.3 (nitrogen trifluoride) at 25 SCCM (standard cubic centimeter per minute) and 0-70% He (helium) at 75 SCCM to etch a layer of PECVD (plasma enhanced chemical vapor deposition) Si.sub.3 N.sub.4 (silicon nitride). The etching takes place at 200 mtorr to 5 torr pressure and 50-400 watts RF power.

Abstract: Wide color range display systems comprising integrated, phase modulated light from three light emitting diode (LED) pixels. Each pixel comprises a large number of LED chips arranged compactly to provide a discrete element light source of sufficient output to be viewed as a point source of light from a substantial distance. The arrays of pixels are placed in a matrix of a type typically used in scoreboards, message centers and other large display systems, although the various combinations, subcombinations, and elements are not limited to such uses. Each pixel is mounted in a molded package which may include a transparent lens covering and sufficient number of connecting leads to provide for the number of colors of LEDs contained in the pixel array. Each pixel is placed in a mounting fixture which also accommodates the necessary electrical connections to multiplexed driving circuitry.

Abstract: Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuation on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block.

Abstract: A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

Abstract: A long useful life, light permeable cover of pigmented, injection-molded silicone rubber for elastic manual placement over and self-retention on a light source enclosure. The cover, due to memory, is self-biasing and self-retaining upon the light source enclosure against inadvertent removal and may be used in large multicolor, automatically programmable, electrically changeable, broad spectrum displays, such as scoreboards.

Abstract: A method is disclosed for operating a real-time multirate and discrete even computer system for simulation and automatic code generation of modelled systems requiring both expert system technology and conventional algorithms. Simulation of a system to be modelled proceeds on data inputs to yield outputs as responses of the simulated system to data inputs for assembling an organized catalog of blocks, both conventional and expert system, based on the operational rates and time skews. These blocks can be assembled for automatic code generation so that all blocks operating with identical rates and time skews can be organized within a single subsystem. Code is then generated for each subsystem, including code for a scheduler to run the entire system thus modelled. Each expert system block generates its own inference engine, and set of parameters representing the knowledge base, and storage allocation for the data base.

Abstract: Disclosed is a high density NOR type read only memory data cell and reference cell network, in which every single data cell of the data cell network is comprised of a MOSFET the gate of which is connected to a wordline and the source and drain of which are selectively connected through buried N+ to a bitline and a voltage source (ground line or power line) permitting the sources of same group of MOSFETs to be connected together through a buried N+ and the drains of which to be connected together through another buried N+ to form a NOR type of structure so as to eliminate possible contacts and reduce space occupation. The design of reference cell network and the connection of the data cell network eliminate the isolation between different groups of MOSFETs so as to increase the density of data cells and reduce the manufacturing cost. By means of buried N+ bitline connection, the implantation of coding can be made as late as the conventional NAND type to that delivery time can be shortened.