Patents Assigned to Integrated Systems
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Patent number: 5894330Abstract: An adaptive anti-flicker data conversion system for converting picture data in a video graphic adapter for displaying on a television. The conversion system reduces flickers adaptively according to the luminance of a pixel and neighboring pixels one line above and below. Contrast difference and mean value are defined based on the luminance of three neighboring pixels. A contrast ratio is computed by dividing the contrast difference by the mean value. Three threshold values are defined for examining the contrast ratio and selecting an appropriate anti-flicker filter. Pixels having higher contrast ratio are processed with filters having stronger anti-flicker effect. The adaptive anti-flicker method reduces flickers without blurring every pixel in the picture data.Type: GrantFiled: January 23, 1997Date of Patent: April 13, 1999Assignee: Silicon Integrated Systems Corp.Inventors: Chien-Hsiu Huang, Ching-Mei Huang
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Patent number: 5884346Abstract: Waste recovery device comprising a container (62) for receiving waste, a radially expansible sheath (19) which is disposed about the container (62) and forms a lining within it, a deflecting member (66, 67) arranged to incurve the path of the sheath (19), a mechanism (73-77, 80-82) for feeding the sheath (19) by holding it under tension so as to cause it to close once it contacts the deflecting member (66, 67), and by displacing as desired the sleeve (19) over a predefined distance so as to cause a new section of sleeve to pass into the container (62), and a mechanism (54) for actuating the feed mechanism.Type: GrantFiled: May 15, 1995Date of Patent: March 23, 1999Assignee: Innovation-Ingeniere-Integration-SystemeInventor: Patrick Hengl
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Patent number: 5883984Abstract: A method for contrast enhancement of pixel data of a decompressed color image includes the steps of computing I component values in an HSI color space for the pixel data of the color image, computing an image I component value which is an average of the computed I component values, and enhancing each of the pixel data of the color image according to the image I component value. An apparatus for contrast enhancement of pixel data of a decompressed color image is also disclosed.Type: GrantFiled: October 3, 1996Date of Patent: March 16, 1999Assignee: Silicon Integrated Systems Corp.Inventors: Ching-Mei Huang, Jo-Tan Yao, Hung-Ju Huang
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Patent number: 5884235Abstract: A method and system are disclosed for measuring a temperature of a body in a non-contact mode based on heat flux measurement. The system includes a temperature measurement apparatus to be positioned in close proximity to a body for measuring the temperature of the body. The temperature measurement apparatus comprises a thermally conducting element, a first and a second temperature sensor, and a temperature modulation arrangement. The first and second temperature sensors are mounted in the conducting element and each measures a temperature of the conducting element. The temperature modulation arrangement modulates the temperature of the conducting element until the temperatures at the first and the second temperature sensors are substantially the same. When these temperatures are equalized, heat flux into the conducting element is zero and the temperature of the conducting element represents the temperature of the body. The apparatus thus enables accurate non-contact temperature measurement of a body.Type: GrantFiled: December 17, 1996Date of Patent: March 16, 1999Assignee: Integrated Systems, Inc.Inventor: Jon L. Ebert
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Patent number: 5825777Abstract: The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware.Type: GrantFiled: June 21, 1996Date of Patent: October 20, 1998Assignee: Creative Integrated Systems, Inc.Inventors: James A. Komarek, Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman
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Patent number: 5825219Abstract: A method for asserting signals onto an output line connected to a passive external pull-up resistor by using a fast edge rate signal driver is provided. The fast edge rate signal driver has first, second and third pull-down predrivers, first, second and third pull-up predrivers, first and second delay elements, and first, second and third output devices, and a PMOS and an NMOS current controller, and each of the output devices has one output terminal coupled to each other forming the output line.Type: GrantFiled: February 21, 1997Date of Patent: October 20, 1998Assignee: Silicon Integrated SyStem Corp.Inventor: Cheng-Hsien Tsai
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Patent number: 5812461Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.Type: GrantFiled: October 29, 1996Date of Patent: September 22, 1998Assignee: Creative Integrated Systems, Inc.Inventors: James A. Komarek, Clarence W. Padgett, Robert D. Amneus, Scott B. Tanner
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Patent number: 5793698Abstract: The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.Type: GrantFiled: April 22, 1997Date of Patent: August 11, 1998Assignee: Creative Integrated Systems, Inc.Inventors: James A. Komarek, Scott B. Tanner, Clarence W. Padgett, Jack L. Minney
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Patent number: 5761718Abstract: An algorithm for conditionally pre-fetching data for DRAM access is disclosed. A similar pattern of performing successive block reads of DRAM data in the execution of several types of instructions in a computer system is determined by analyzing CPU signals. These instructions repeatedly read blocks of data from a local memory area. Additional writes to memory or an input/output port may intervene between the repeated block reads. By using the pattern as a condition for pre-fetching data from DRAM into a high speed memory buffer of a memory controller, consecutive memory reads can be completed with zero wait state. The penalty incurred by unconditional pre-fetching of DRAM data is minimized. The conditional pre-fetching mechanism is applicable to other computer peripheral devices.Type: GrantFiled: August 30, 1996Date of Patent: June 2, 1998Assignee: Silicon Integrated Systems Corp.Inventors: Yung Cheng Lin, Shih Jen Chuang
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Patent number: 5748904Abstract: A method and system for compressing graphic data by dividing the data into segments is disclosed. The size of the divided segment is programmable. A frame buffer partitioned into a compressed frame buffer and an uncompressed frame buffer stores graphic data. Each segment of the graphic data is compressed by three different algorithms that encode the graphic data as a plurality of code-words. Each code-word for the segment is taken from the algorithm that can compress the largest number of pixels in the code-word. A header is used to indicate the number of code-words and the compression method used in each code-word. The total number of bytes obtained from the compression of a segment is compared to a pre-defined limit to determine if the compression of the segment is successful. The successfully compressed data of a segment are written to the compressed frame buffer. A compression status flag buffer is used to identify if a segment is compressed or not.Type: GrantFiled: September 13, 1996Date of Patent: May 5, 1998Assignee: Silicon Integrated Systems Corp.Inventors: Hung-Ju Huang, Jo-Tan Yao, Chung-Heng Chen
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Patent number: 5731809Abstract: An adaptive display memory management system for using idled display memory in a video graphics adapter card as extra system memory of a personal computer is presented. By means of hardware implementation, the memory management system manages the video display memory according to the video display mode and takes advantage of the idled display memory in forming virtual system memory for the computer, so that the working space of executing a user program is increased and the system performance of the computer is enhanced.Type: GrantFiled: July 10, 1995Date of Patent: March 24, 1998Assignee: Silicon Integrated Systems Corp.Inventors: Hung-Ming Lin, Mao-Yuan Ku
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Patent number: 5730210Abstract: A heat sink having an assembling device using mechanical characteristics of resilience or flexibility so as to effectively fasten a heat sink. In one embodiment, this invention comprises a chassis having a heat dissipating surface, a plurality of fastening holes formed on the chassis, and fastening bolts and helical springs corresponding to the fastening holes, wherein the fastening bolts each further comprise a mushroom-shaped insertion end. In another embodiment, the heat sink comprises a chassis having a heat dissipating surface and a fastening seat for fastening the heat sink, wherein the fastening seat is formed of a resiliently curvable and integrally formed sheet and is provided with a pair of hooks each having a V-shaped barb for inserting the invention into holes abutting the chip and pre-formed on a motherboard and for resiliently pressing the heat sink against the chip.Type: GrantFiled: February 24, 1997Date of Patent: March 24, 1998Assignee: Silicon Integrated Systems CorporationInventor: Chih Hsien Kou
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Patent number: 5732035Abstract: An improved precharge timing control is provided by turning off the first one of a series of precharge clocks PC0 by means of discharging a single dummy word line. The dummy word line is comprised of a plurality of dummy word line segments wherein each of the segments are charged in parallel, but discharged in series. The discharge time required of the plurality of word line segments is sufficient to allow discharge of an end of a selected word line in the read only memory to ground. Improved timing with good performance is achieved by turning off the earliest precharge clock PC0 among a series of precharge clocks PC0 and PC1, for example, so that an improved precharge time for the ROM core for a fast process parameter is realized.Type: GrantFiled: September 26, 1996Date of Patent: March 24, 1998Assignee: Creative Integrated Systems, Inc.Inventors: James A. Komarek, Clarence W. Padgett
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Patent number: 5704708Abstract: The apparatus is a lamp assembly with a plurality of bulb assemblies used for data (or similar) display with varying character sizes. The bulb assemblies include a reflector with three bosses. Two of the bosses snap detent engage a lampbank while the third boss extends through the lampbank, attaches to a printed circuit board and serves as a standoff or spacer therefrom. The bulb assemblies further include a louver which snap engages onto the lens to form a lens/louver assembly which hinges and snaps to the reflector. The louver can be used as a handle to remove the lens from the bulb assembly.Type: GrantFiled: April 10, 1996Date of Patent: January 6, 1998Assignee: Integrated Systems Engineering, Inc.Inventors: Robert Dee Barson, Derik Remmelle West
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Patent number: 5682522Abstract: A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.Type: GrantFiled: July 18, 1995Date of Patent: October 28, 1997Assignee: Silicon Integrated Systems Corp.Inventors: Hung-Ju Huang, Hung-Ming Lin
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Patent number: 5678036Abstract: A method for minimizing idle time of a controller in a graphics system, which includes a graphics memory and a graphics accelerating device that interconnects the controller and the graphics memory, is disclosed. The graphics accelerating device includes a command register for storing command signals from the controller therein, and a graphics engine for receiving and executing the command signals stored in the command register one at a time.Type: GrantFiled: May 31, 1995Date of Patent: October 14, 1997Assignee: Silicon Integrated Systems Corp.Inventors: Hung-Ming Lin, Lintien Mei, James Lee
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Patent number: 5650979Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.Type: GrantFiled: September 6, 1996Date of Patent: July 22, 1997Assignee: Creative Integrated Systems, Inc.Inventors: James A. Komarek, Scott B. Tanner, Clarence W. Padgett, Jack L. Minney
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Patent number: 5613419Abstract: A load balancing arm is shown and described as having improved control including a programmable control element and electronic air regulation to provide precise and controllable lifting force on a load. The disclosed load balancing arm responds to slight operator applied force to aid in movement of the load in overcoming system hysteresis, friction and load inertia without requiring the operator to apply a sufficiently large magnitude force to overcome such counteracting forces in the system. The disclosed load balancing arm further includes automatic load weight detection sensors for accommodating variation in load weights while applying a lifting force to the load which substantially equals the weight of the load. This allows the operator to move the load freely throughout a work space.Type: GrantFiled: October 10, 1995Date of Patent: March 25, 1997Assignee: Integrated Systems, Inc.Inventors: Cary M. Pierson, Stephen L. Heston
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Patent number: 5612866Abstract: A code generation system to construct an asynchronous real-time controller for a real-time system with asynchronous subsystems is described. The system includes a software user interface to specify a functional description of a real-time system with asynchronous subsystems. The software user interface includes code construction elements selected from a functional library with a corresponding menu. The menu includes a start-up procedure selection option used to initialize parameters associated with the real-time system, a background procedure selection option to specify a control action to be executed in relation to the real-time system, and an interrupt procedure selection option to specify an operation to be performed in response to an asynchronous interrupt signal. Each of the selection options include a variable block definition tool to read and write values to global variables.Type: GrantFiled: June 24, 1994Date of Patent: March 18, 1997Assignee: Integrated Systems, Inc.Inventors: John Savanyo, Saumil S. Shah
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Patent number: 5608687Abstract: The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active.Type: GrantFiled: November 27, 1995Date of Patent: March 4, 1997Assignees: Creative Integrated Systems, Inc., Rocoh Company Ltd.Inventors: James A. Komarek, Clarence W. Padgett, Scott B. Tanner, Shin-ichi Kojima, Jack L. Minney, Motohiro Oishi, Keiji Fukumura, H. Nakanishi