Abstract: A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.

Abstract: A fully differential double edge triggered flip-flop stores and outputs first and second fully differential input values on leading and trailing edges of a clock. The flip-flop includes a first fully differential master circuit, a second fully differential master circuit and a fully differential slave circuit. The first master circuit stores the first input value during the period from the leading edge to trailing edge of the clock. The second master circuit stores the second input value during the period from the trailing edge to leading edge of the clock. The slave circuit is electrically connected to outputs of the first and second master circuits. The slave circuit includes a second repeater as an output end of the flip-flop, outputs the first input value on the trailing edge of the clock, and outputs the second input value on the leading edge of the clock.

Abstract: A multi-layered substrate having built-in capacitors is used to decouple high frequency noise generated by voltage fluctuations between a power plane and a ground plane of a multi-layered substrate. At least one kind of dielectric material, which is filled in through holes between the power plane and the ground plane, with high dielectric constant is used to form the built-in capacitors.

Abstract: This invention provides a method for forming a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A multi-layered substrate having built-in capacitors is disclosed. The substrate comprises at least one high permittivity of dielectric material filled in the through holes between the power plane and the ground plane so as to form capacitors. The built in capacitors are to decouple high frequency noise due to the voltage fluctuation.

Abstract: This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Abstract: The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals.

Abstract: A non-stalling pipeline tag controller includes cascaded source and holding registers coupled respectively to an external input unit and a data memory module. A tag memory module includes a tag memory unit for storing tags to memory data in the data memory module, and a first comparator unit that generates a first decision signal to indicate whether the source tag in the source register matches with one of the tags in the tag memory unit. A status module includes a second comparator unit that generates a second decision signal to indicate whether the source tags stored in the source and holding registers match with one another, and a decision unit that compares the first and second decision signals and that generates a third decision signal to indicate occurrence of a cache hit or cache miss condition.

Abstract: A computer system includes an integrated core and graphic controller device having a core logic controller portion and a graphic controller portion, a system memory pool, and a stand-alone frame buffer memory pool separate from the system memory pool. A first memory data bus interconnects the integrated core and graphic controller device and the system memory pool. A second memory data bus interconnects the integrated core and graphic controller device and the frame buffer memory pool. A memory address and control signal bus interconnects the integrated core and graphic controller device, the system memory pool and the frame buffer memory pool.

Abstract: A bond pad structure and a method of fabricating such structure are disclosed in the invention. The bond pad structure is formed over a predetermined area defined on a semiconductor substrate. The bond pad structure includes at least two metal layers formed over the predetermined area and at least one sub-structure combination layer which each is formed over the predetermined area and formed between two corresponding first metal layers. Each sub-structure combination layer includes a dielectric layer formed over the predetermined area, formed-through via openings with special disposition on the dielectric layer, a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs.

Abstract: The present invention provides a method for fabricating a metal capacitor. A first level metal layer is formed on a substrate. Then, the first level metal layer is patterned to concurrently form a first metal line and a second metal line. The second metal line defines a metal capacitor region and is used as a lower electrode of the metal capacitor. Then, an insulating layer is conformably formed on the substrate, the first metal line, and the second metal line. A first intermetal dielectric layer is formed on the insulating layer. Then, the first intermetal dielectric layer is subjected to planarization treatment such that the planarization treatment finally exposes the insulating layer. Finally, a third metal line is formed on the insulating layer in the metal capacitor region such that the third metal line is used as the upper electrode of the metal capacitor.

Abstract: A VGA to TV data transformation system uses a background-based adaptive flicker reduction method. Information in a picture displayed on a screen of a monitor is divided as graphic and video information. Graphic information which includes cursor, graphic data, and sub-picture of video data in video information is prone to flicker. A background-based adaptive flicker reduction is applied to pixels in regions containing graphic information. A current pixel and the adjacent pixels directly above and below the current pixel are used to compute Mean and Diff values. The background state of a current pixel is determined by comparing the Mean value with a threshold value. The background state, the Mean value and the Diff value are then used to select a flicker reduction mode that may be strong reduction, median reduction, mild reduction or no reduction. An anti-flicker pixel is generated according to the flicker reduction mode.

Abstract: A crystal oscillator circuit includes an oscillator gain stage, an intermediate amplifier, a high frequency noise filter, an output buffer and a power supply noise filter. The oscillator gain stage has a voltage reduction circuit for adjusting the voltage swing level of a generated clock signal. The generated clock signal is amplified by the intermediate amplifier and the high frequency noise filter filters the amplified signal. The power supply noise filter removes noise in the power supplied to the oscillator gain stage and the intermediate amplifier. The high frequency noise filter has two noise filtering circuits and a time-delay circuit. The time-delay circuit prevents two transistors in the output buffer from being turned on simultaneously to avoid large short circuit current and save power.

Abstract: A remote plasma generator, coupling microwave frequency energy to a gas and delivering radicals to a downstream process chamber, includes several features which, in conjunction, enable highly efficient radical generation. In the illustrated embodiments, more efficient delivery of oxygen and fluorine radicals translates to more rapid photoresist etch or ash rates. A single-crystal, one-piece sapphire applicator and transport tube minimizes recombination of radicals in route to the process chamber and includes a bend to avoid direct line of sight from the glow discharge to the downstream process chamber. Microwave transparent cooling fluid within a cooling jacket around the applicator enables high power, high temperature plasma production. Additionally, dynamic impedance matching via a sliding short at the terminus of the microwave cavity reduces power loss through reflected energy. At the same time, a low profile microwave trap produces a more dense plasma to increase radical production.

Abstract: The present invention concerns a method for stripping the photoresist layer and the crust from a semiconductor. The crust has been formed with as a result of an ion implantation step, wherein the method comprises an ion assisted plasma step using a mixture of water vapour, helium and a F-containing compound in which radicals are generated, and the step of contacting said photoresist layer and crust with said radicals to remove said photoresist layer and crust from said semiconductor surface. Said plasma step is preferably an ion assisted plasma step.

Abstract: This invention provides a method for forming a metal capacitor with a damascene process. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by the following steps. An opening for a capacitor is formed in a second insulator. Then, a first metal layer, a dielectric layer and a second metal layer are conformally formed in the opening on the second insulator. The stacked layers are subjected to a chemical mechanical polishing process until the second insulator is exposed. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: The present invention is for a system for tracking and graphically displaying the positions of vehicles in a fleet, and interacting with the vehicles from a base station. The vehicles in the fleet are equipped with a G.P.S. receiver and communicate the G.P.S. information to a base station. A receiver at the base station receives the information. A computer system connected to the receiver then uses this information to display the position of the vehicle using mapping and tracking software. The system also includes update software which updates text data in a database, updates the graphical representation of the vehicle, and bidirectionally and dynamically links and integrates the text data with the graphical representation of a vehicle. The text data in the database includes information relating to the vehicle, the driver, the schedule of the fleet as well as information relating to the fleet.

Abstract: A ferroelectric ceramic for use as a pyroelectric is provided. In a disclosed embodiment, the ceramic has the composition: Pb1+&dgr;{[(Mg⅓Nb⅔)y(Zr1−xTix)1−y]1−zAz}O3 where: 0.05≧67 ≧0 0.42≧x>0 0.42≧y>0 0.05≧z>0 and wherein A is a cationic multivalent octahedral site substituent. The ferroelectric ceramic is useful as an active pyroelectric material in infrared detecting devices.

Abstract: A cache memory system includes a main memory controller for retrieving memory data from a main memory unit, a cache memory for writing the memory data retrieved by the main memory controller therein, and a tag memory module for detecting presence of a cache hit condition, indicating that an address signal received thereby has a corresponding data entry in the cache memory, or a cache miss condition, indicating a need for accessing the main memory unit. An address queue of a read data controller receives a cache memory address corresponding to the address signal from the tag memory module, and provides the cache memory address to the cache memory to control reading of the memory data from the cache memory.

Abstract: An integrated circuit device is adapted for use in a computer system that includes a processing unit, a host bus connected to the processing unit, an input/output bus, a peripheral device connected to the input/output bus, a monitor, and a system memory. The integrated circuit device includes a core controller adapted to be connected to the host bus, a bus bridge connected to the core controller and adapted to be connected to the input/output bus, a graphical controller connected to the core controller and the bus bridge and adapted to be connected to the monitor, and a unified memory control unit connected to the core controller and the graphical controller and adapted to be connected to the system memory.