Patents Assigned to Integrated Systems
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Patent number: 6317813Abstract: In a memory controller system, a method for granting a system memory by a memory request arbitrator to a request among a plurality of pending memory access requests is provided. The plurality of the memory access requests includes Rfrsh_Hreq, Crt_Hreq, Group AB, Crt_Lreq and Rfrsh_Lreq and are respectively asserted by a host control circuitry and/or a graphical control circuitry which are implemented and integrated on a single monolithic semiconductor chip. The host control circuitry and the graphical control circuitry shares the system memory and the memory request arbitrator includes a refresh queue and the graphics control circuitry includes a CRT FIFO. The method prioritizes the plurality of the memory access requests in order of Rfrsh_Hreq>Crt_Hreq>Group AB>Crt_Lreq>Rfrsh_Lreq.Type: GrantFiled: May 18, 1999Date of Patent: November 13, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Jen-Pin Su, Chun-Chieh Wu, Wen-Hsiang Lin, Tsan-hui Chen
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Patent number: 6304608Abstract: A method for reducing baseband tones and intermodulation distortions in a multibit sigma-delta converter employing dynamic element matching is disclosed. An N-level sigma-delta analog-to-digital converter includes an analog loop filter, an N-level quantizer, an element selection logic, an internal N-level digital-to-analog converter (DAC), and a decimation filter, where N is an integer greater than two. Adding k extra unit elements to the internal N-level DAC, which totally comprises (N−1+k) unit elements, can shift the sigma-delta modulator tones and intermodulation distortions outside the baseband with no change to the quantization levels of the internal N-level DAC, where k is a positive integer. A cyclical selection of (N−1+k) unit elements in the internal N-level DAC is in accordance with an element selection logic which receives an output of the N-level quantizer and produces a set of control signals for the element selection of the internal N-level DAC.Type: GrantFiled: November 4, 1998Date of Patent: October 16, 2001Assignees: Tai-Haur Kuo, Taiwan Semiconductor Manufacturing Company, Silicon Integrated Systems Corp.Inventors: Kuan-Dar Chen, Tai-Haur Kuo
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Patent number: 6304482Abstract: An apparatus of reducing power consumption of a single-ended Static Random Access Memory (hereinafter referred as SRAM) is provided. The apparatus consists of at least an extra column of status memory cell and a majority detector by which a bit status of a written data is detected and by which the value of the bit status is written into the extra column of status memory cell. The apparatus further includes a data scrambler by which the written data is converted into a storage data with a minority of 0 bits based on the value of bit status and by which the storage data is written into the main single-ended SRAM cell. The apparatus further includes a data de-scrambler by which the storage data in the main single-ended SRAM cell is converted into its original format based on the value of bit status stored in the extra column of memory cell and by which the data in its original format is output.Type: GrantFiled: November 21, 2000Date of Patent: October 16, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Hung-Ming Lin, Hung-Ta Pai
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Patent number: 6297472Abstract: A welding system and method of use which allows a single welding operator to perform quick, easy and high quality vertical welds. The welding system comprises a welding fixture with a pair opposing, positionally adjustable welding shoes, and lock screws for attaching to a workpiece such as an I-beam. The welding fixture is located adjacent the end of an articulating boom, and a welding torch and oscillator are included on the welding fixture. A rotary straight wire feeder removes the cant and helix from welding wire as it is fed to the welding torch. The welding torch prevents welding wire from fusing to a guide tube in a manner which would interrupt a welding operation. The invention includes a distributed welding control system comprising a plurality of controller modules interfaced with a common bus. The control system allows a welding operator to program automated welding cycles for various welding operations.Type: GrantFiled: April 10, 1998Date of Patent: October 2, 2001Assignee: Aromatic Integrated Systems, Inc.Inventors: William L. Bong, Charles A. Bock, Michael D. Glenn-Lewis
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Patent number: 6292201Abstract: An integrated circuit device is adapted for use in a computer system that includes a processing unit, a host bus connected to the processing unit, an input/output bus, a peripheral device connected to the input/output bus, a monitor, and a system memory. The integrated circuit device includes a core controller adapted to be connected to the host bus, a bus bridge connected to the core controller and adapted to be connected to the input/output bus, a graphical controller connected to the core controller and the bus bridge and adapted to be connected to the monitor, and a unified memory control unit connected to the core controller and the graphical controller and adapted to be connected to the system memory.Type: GrantFiled: November 25, 1998Date of Patent: September 18, 2001Assignee: Silicon Integrated Systems CorporationInventors: Joseph Chen, Hung-Wen Chen, Michael Chen
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Patent number: 6287071Abstract: An apparatus is adapted for picking-up an integrated circuit component and is adapted to be connected to an air pump. The apparatus includes a retaining block formed with a first pipe hole and a washer receiving recess for receiving a washer. An air pipe is formed with a radially and outwardly extending rim flange at a junction of upper and lower pipe sections thereof. The lower pipe section extends sealingly through a second pipe hole in the washer and further through the first pipe hole such that the rim flange rests on top of the washer in the washer receiving recess, such that a distal lower end of the lower pipe section projects downwardly relative to the retaining block, and such that a distal upper end of the upper pipe section extends outwardly of the washer receiving recess and projects upwardly relative to the retaining block.Type: GrantFiled: June 5, 2000Date of Patent: September 11, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Lai-Fue Hsieh, Yi-Chang Hsieh, Ching-Jung Huang, Mu-Sheng Liao
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Patent number: 6282595Abstract: A method for testing an interface card used with a computer is provided. The method includes steps of (a) providing the computer with a read-only memorizing device for saving a testing program therein, (b) starting the computer, (c) detecting whether there exists the interface card electrically connected to the computer, (d) causing the computer to change from a first mode to a second mode when the interface card is detected, and (e) executing the testing program to test the interface card.Type: GrantFiled: August 4, 1998Date of Patent: August 28, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Cheng-Feng Pan, Wen-Cheng Lin
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Patent number: 6271851Abstract: The present invention discloses a method and system, which discards invalid pixels by using cache memories storing depth values of all pixels having inputted which satisfy a Z Test Mode. The present invention is applied in a three-dimensional graphic system, and uses a plurality of pre-test units to process input pixels in a parallel manner to avoid system performance degeneration due to sequential execution used in prior art. The plurality of pre-test units read the depth values stored in a pre-test Z cache in the system and compare them with the depth values of input pixels being processed according to the Z Test Mode. If the answer is yes, the input pixels are discarded. Otherwise, the content of the pre-test Z cache is updated.Type: GrantFiled: June 20, 2000Date of Patent: August 7, 2001Assignee: Silicon Integrated Systems CorporationInventors: Chien-Chung Hsiao, Tsung-Feng Lee
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Patent number: 6263830Abstract: A remote plasma generator, coupling microwave frequency energy to a gas and delivering radicals to a downstream process chamber, includes several features which, in conjunction, enable highly efficient radical generation. In the illustrated embodiments, more efficient delivery of oxygen and fluorine radicals translates to more rapid photoresist etch or ash rates. A single-crystal, one-piece sapphire applicator and transport tube minimizes recombination of radicals in route to the process chamber and includes a bend to avoid direct line of sight from the glow discharge to the downstream process chamber. Microwave transparent cooling fluid within a cooling jacket around the applicator enables high power, high temperature plasma production. Additionally, dynamic impedance matching via a sliding short at the terminus of the microwave cavity reduces power loss through reflected energy. At the same time, a low profile microwave trap produces a more dense plasma to increase radical production.Type: GrantFiled: April 11, 2000Date of Patent: July 24, 2001Assignee: Matrix Integrated Systems, Inc.Inventors: Mohammad Kamarehi, Gerald M. Cox
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Patent number: 6256262Abstract: A memory device includes a global decoder circuit and two memory cell array devices, each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit. Each of two data input buffers is disposed at a third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, and is coupled to the respective one of the memory cell arrays. A write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. A write clock buffer is disposed adjacent to the third side of the global decoder circuit, and is coupled to the data input buffers. A read control circuit is coupled to and is disposed adjacent to a fourth side of the global decoder circuit. Each of two multiplexer sets is coupled to bit lines of a respective one of the memory cell array devices.Type: GrantFiled: August 8, 2000Date of Patent: July 3, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Hsing-Yi Chen, Jo-Yu Wang, Hsin-Kuang Chen, Jyh-Ming Wang
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Patent number: 6251768Abstract: A method of arranging staggered bond pads layers for effectively reducing the size of a die. The sizes of different bond pad layers are reduced gradually from the upper layer to the lower layer, while the sizes of traces in different layers are increased from the upper layer to the lower layers. The size of the first layer is specified and determined by the specification of a wire bonder. The reduction of different bond pad layers may be linear or nonlinear.Type: GrantFiled: March 8, 1999Date of Patent: June 26, 2001Assignee: Silicon Integrated Systems Corp.Inventor: Wei Feng Lin
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Patent number: 6239433Abstract: Sensors using detector arrays (1) are intended for identifying events within a scene (12). A sensor comprising an array of pyroelectric infrared detectors (1) is mounted directly onto an integrated readout circuit (2) so that each of its elements is in electrical contact with one of the inputs to the readout circuit. The detector array (1) on its readout circuit (2) is positioned at the focus of an infrared transmitting lens (11) so that an image of a scene (12) is formed on the array. The readout circuit (2) and array (1) are enclosed in a package (18) which is connected via a circuit board (19) to a microprocessor (20). The microprocessor (20) and readout circuit (2) work together to detect the occurrence and position of events within a scene (12). Application examples are the detection and identification of location of flames or intruders within the field of view.Type: GrantFiled: January 13, 1998Date of Patent: May 29, 2001Assignee: Infrared Integrated Systems. Ltd.Inventor: Stephen George Porter
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Patent number: 6239698Abstract: When an array of thermal detectors with appropriate read-out means is used as a sensor to detect events such as intruders or fire, it may be disabled accidentally or deliberately by placing a mask over the array to shield it from the scene. The act of placing a mask over the array induces a simultaneous transient signal from all of the detectors, or at least a majority of the detectors, and is followed by a period when those detectors give rise only background noise or clutter. The characteristics of these signals is used to generate a warning signal to indicate that the sensor has been disabled.Type: GrantFiled: July 12, 1999Date of Patent: May 29, 2001Assignee: Infrared Integrated Systems, Ltd.Inventors: Stephen George Porter, Bryan Lorrain Humphreys Wilson, Stephen Hollock
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Patent number: 6239640Abstract: The present invention provides a double edge trigger D-type flip-flop which can be both triggered at the rising edge and falling edge of a clock. That is to say, the double edge trigger D-type flip-flop of the present invention can access data twice in a clock cycle. Therefore, the double edge trigger D-type flip-flop of the present invention is capable of providing a double accessed data amount than that of a conventional rising (or falling) edge trigger D-type flip-flop, thereby significantly increasing the efficiency of the system.Type: GrantFiled: April 6, 1999Date of Patent: May 29, 2001Assignee: Silicon Integrated Systems CorporationInventors: Stanley Liao, Horng-Jyh Liu, Hsing-yi Chen
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Patent number: 6228773Abstract: Workpieces, such as, semiconductor wafers, are continuously manufactured by repetitively alternately switching a common radio frequency power source between a plurality of downstream or in-chamber processing reactors and actively processing one workpiece in a vacuum in an operating one of the processing chambers while simultaneously executing with a robot at atmospheric pressure the overhead tasks relative to next processing another workpiece in the other processing chamber. The active processing of the workpieces in alternate chambers does not overlap, and the robot starts and completes all of its preparatory tasks during the active processing step during the time when a chamber's door is closed thereby providing virtual zero overhead. System architecture allows eliminating all redundant components other than the dual chambers which operate in parallel. For a modest cost increase for the second chamber throughput is trebled and overall costs significantly reduced.Type: GrantFiled: April 14, 1998Date of Patent: May 8, 2001Assignee: Matrix Integrated Systems, Inc.Inventor: Gerald M. Cox
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Patent number: 6226704Abstract: The present invention provides a method and apparatus for performing bus transactions orderly and concurrently in a bus bridge. To meet the ordering rules, the invention adopts a HOLD/HLDA handshaking mechanism to control the flow of transactions in the bus bridge. When both HOLD and HLDA signals are asserted, the bus bridge holds the transaction processed in one direction and then the bus bridge is ready to process the transaction from another direction. That is, the bus bridge first controls the transaction flowing in one direction whenever there is request coming from another direction, wherein the HOLD signal is asserted simultaneously. Upon receipt of the HLDA signal indicating that the transaction flow has been completely held in one direction, the bus bridge allows the transaction to flow from another direction by granting the request agent bus ownership. The present invention also provides a method to avoid deadlock. The bus bridge retries transactions stalling the bus in two cases.Type: GrantFiled: December 1, 1998Date of Patent: May 1, 2001Assignee: Silicon Integrated Systems CorporationInventors: Wan-Kuang Wang, Wen-Hsiang Lin, Michael T. H. Chen
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Patent number: 6215764Abstract: A method and apparatus for detecting the link status of a network device in a computer system. An automatic link status detection mechanism allows a system to operate intelligently in a normal operation mode if the link status is on, or a suspend mode if the link state is down. The mechanism includes an auto link poll controller and a polling cycle generator for generating a sequence of polling cycles to query the link status of the network device. A media independent interface management frame having a preamble field is generated in a polling cycle. Because of the improved preamble field, it is to assure that an exact polling cycle is complete when a polling cycle is issued to the physical layer of the network device.Type: GrantFiled: June 4, 1998Date of Patent: April 10, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Yih-Sheng Wey, Hui-Chen Hsieh, Yen-Jiuan Chao
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Patent number: 6204676Abstract: A testing apparatus for testing a ball grid array (BGA) device, includes a movable carrier which has a top face recessed to form a cavity of square shape to receive the BGA device. A centering member is disposed at a center part of a cavity bottom face of the cavity to center a squarely looped array of voltage source solder balls formed at a bottom face of the BGA device, relative to the center part of the cavity bottom face. The centering member projects upward from the cavity bottom face to engage and prevent positional deviation of the squarely looped array of the voltage source solder balls when the BGA device is seated on the cavity bottom face. The testing apparatus further includes a testing circuit unit, a surface mount matrix disposed on top of the testing circuit unit, and a hollow frame member mounted on top of the surface mount matrix.Type: GrantFiled: May 10, 1999Date of Patent: March 20, 2001Assignee: Silicon Integrated Systems Corp.Inventors: Yi-Chang Hsieh, Lai-Fue Hsieh, Mu-Sheng Liao
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Patent number: 6185573Abstract: The present invention is an automated system to input text, audio and video data, to integrate the storage of the data at a central location, to initiate queries of search criteria to the central location from remote locations, and to dynamically transmit text, audio and video data to the remote locations in accordance with the search criteria.Type: GrantFiled: April 22, 1998Date of Patent: February 6, 2001Assignee: Millenium Integrated Systems, Inc.Inventors: Vincent Angelucci, Stephen Madaras
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Patent number: 6182298Abstract: A latching device eg for attaching a breathing mask to an aircrew helmet, has detents (20) on a receptacle portion (10), and teeth (32) on carriers (30,31) supported for arcuate movement in an insert portion (14) and supported (eg at 33) so that bending loads on the carriers are substantially avoided.Type: GrantFiled: June 24, 1996Date of Patent: February 6, 2001Assignee: Helmet Integrated Systems Ltd.Inventor: Ian Trevor Dampney