Abstract: Method and system for determining the effects of variation of N statistically distributed variables (N≧1) in a fabrication process for semiconductor and other electronic devices by constructing and using an N-variable model function G(x1, . . . ,xN) to model the process. A sequence of orthogonal polynomials is associated with each probability density function Pi(xi) for each variable xi. These orthogonal polynomials, and products of these polynomials, are used to construct the model function G(x1, . . . ,xN), having undetermined coefficients. Coefficient values are estimated by results of measurements or simulations with variable input values determined by the zeroes (collocation points) of selected orthogonal polynomials. A Monte Carlo process is applied to estimate a probability density function associated with the process or device. Coefficients whose magnitudes are very small are used to identify regions of (x1, . . . ,xN)-space where subsequent Monte Carlo sampling may be substantially reduced.

Abstract: A power saving clock buffer comprises a first control stage installed between a clock output and a first switch stage for controlling the state of the first switch stage. A second switch stage installed between the clock output and a second switch stage for controlling the state of the second switch stage. A clock input stage is formed by connecting an PMOS with a NMOSs, and is installed between a clock input and the first and second switch stages and is connected to the clock output through a phase inverting logic circuit. By the aforementioned circuit structure, the clock circuit will stop working as the related circuit does not work and, therefore, the power is saved and a high reliability is attained.

Abstract: A tray is adapted to receive a plurality of ball grid array devices therein, and includes a base plate having a device-receiving portion and a peripheral portion around the device-receiving portion. The device-receiving portion has a top side formed with a device-receiving recess. The top side of the device-receiving portion is further formed with a partition unit in the device-receiving recess for dividing the device-receiving recess into a plurality of cavities adapted for receiving the ball grid array devices respectively therein. The device-receiving portion further has a bottom side formed with a plurality of openings. Each of the openings is aligned with a corresponding one of the cavities and is adapted to receive an array of ball contacts formed on a bottom side of the ball grid array device that is disposed in the corresponding one of the cavities therein.

Abstract: The present invention generally relates to the conversion of a picture data in an interlaced format to a progressive format, and more particularly, to an adaptive edge-based scan line interpolation method and apparatus for improving the picture quality in a display system. The present invention provides a method and apparatus for converting interlaced scanning images to progressive images by using simple motion detection procedure and adaptive edge-interpolation. Therefore, the present invention is capable of performing the interlaced-to-progressive conversion with less hardware and buffer cost. Besides, the present invention performs the motion detection by examining the 1-D (one-dimension) pixel array at the adjacent fields. Therefore, the computation of the interlaced-to-progressive conversion of the present invention is less complex than the prior art. Furthermore, the video image of the present invention has a sharper video image with edge preservation and flicker reduction.

Abstract: A method for generating information for producing a pattern, defined by design information on a medium, using at least one direct-writing pattern generating process, which first provides the design information and then calculates correction data based on the provided design information and depending on the pattern generating process which corrects pattern faults in the pattern to be generated which were caused by the pattern generating process. The design and correction information is then separately provided to the direct-writing pattern generating process for its activation.

Abstract: In a method and apparatus for detecting a wake packet among data bytes in a packet frame issued by a network device, the data bytes in the packet frame are initially compared with a sync byte to detect start of a synchronization stream of the wake packet. The number of consecutive sync matches of the data bytes in the packet frame with the sync byte is counted, and a partial match flag is set upon detection that the number of consecutive sync matches has reached a predetermined number of sync duplications of the sync byte to indicate that the synchronization stream has been detected in the packet frame. When the partial match flag is set, the data bytes that follow the synchronization stream in the packet frame are compared with address bytes of a destination address assigned to a sleeping node.

Abstract: A contactor system is adapted for use when testing a ball grid array (BGA) device, and includes a conductive socket that is retained on a testing board and that establishes a ground connection therewith. The socket is formed with a receiving space adapted for receiving the BGA device therein. An insulating guide unit is mounted on the socket in the receiving space and is adapted to guide loading movement of the BGA device into the receiving space via an open top section of the latter and to prevent undesired electrical contact between the socket and the BGA device. A surface mount matrix is disposed on top of the testing board and is clamped between the socket and the testing board. The surface mount matrix is accessible via an open bottom section of the receiving space, and is adapted to contact solder balls on the BGA device directly so as to establish electrical connection between the BGA device and testing circuit layout on the testing board.

Abstract: The LED modular display system includes a frame of support members of triangular cross sections. The frame supports a plurality of LED display modules which include a generally planar front face upon which an array of LEDs is placed. The LED display modules further include inwardly tapered vertical sidewalls and horizontal upper and lower trapezoidal faces. The support members of triangular cross section fit flush against the inwardly tapered vertical sidewalls of the LED display modules. Fasteners on the inwardly tapering walls of the LED display modules engage complementary elements on the support members.

Abstract: A method and system for permitting a software-based executive to execute concurrently with a hardware-based executive. The software-based executive allocates hardware executive tasks, hardware executive interrupts, software executive tasks, and software executive interrupts to defined execution spaces available on a microprocessor having a hardware-based executive. Applications control hardware-based executive tasks and interrupts through a hardware executive application programming interface (API), and software-based executive tasks through a software executive API. Applications share the hardware executive API functions for interrupt installation and management. The invention allocates all hardware executive interrupts to a high priority interrupt execution space, and all hardware executive tasks to a high priority queue. All software executive interrupts are allocated to low priority interrupts, and all software executive tasks are allocated to a low priority queue.

Abstract: A chip carrier for carrying a chip is disclosed.

Abstract: Apparatus and methods for AC power regulation primarily intended for inductive loads (e.g., fluorescent lights, motors, etc.) which provide substantial reduction in power consumption while also providing a leading power factor, reduced harmonic distortion, reduced crest factor and reduced noise. The system is self-adjusting for a wide range of loads and can reduce power consumption by 25 percent in lighting loads while producing minimal reduction in light output. The system utilizes a Triac and parallel capacitor bank in series with the load. The Triac is turned on in response to a near-zero differential voltage measured across the Triac and is turned off near the peak of each AC half cycle by shunting current around the Triac. The capacitor absorbs the inductive turn-off voltage spike caused by the collapsing magnetic field in the ballast at the instant of Triac turn-off. This energy, in turn, provides longer on-period for the lamp, thereby permitting more light and increased operating efficiency.

Abstract: A first device provides a repetitive count of time. A second device indicates in each successive count of time by the first device during the processing apparatus operation whether the processing apparatus has processed data for at least a first particular percentage of time in each such successive time count. A third device indicates in each successive count of time by the first device during the processing apparatus operation whether the processing apparatus has processed data for at least a second particular percentage of time in each such successive time count where the second particular time percentage is less than the first particular time percentage. A power supply provides power to the processing apparatus during the time that the apparatus is processing data.

Abstract: An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

Abstract: A small and economically fabricated CMOS voltage controlled crystal oscillator is provided by coupling three inverter amplifiers in series with a regenerative crystal controlled feedback loop. The first and second CMOS inverters have output nodes whose impedances are modified by a CMOS impedance modulating circuit. Also coupled to each of these two output nodes is a CMOS transistor shunt capacitor. The impedance of the output node is modified according to the magnitude of a voltage control signal applied to the CMOS modulating circuits. The self-bias of the modulating circuits is maintained substantially constant by adjusting the gate drive in each of the modulating circuits according to gate drives derived from a dummy modulating circuit.

Abstract: A cell-sensing unit is applied to a memory device having a cell associated operably with a complementary pair of bit lines and a word line. The cell-sensing unit includes a current sense amplifier having a first input side adapted to be connected to the bit lines, and a first output side, and a voltage amplifier having a second input side connected to the first output side of the current sense amplifier, and a second output side. The current sense amplifier is capable of magnifying a difference between currents flowing through the bit lines during a read cycle of the cell, and generates a corresponding voltage difference at the first output side. The voltage difference is received by the voltage amplifier at the second input side, and has a magnitude sufficient to enable the voltage amplifier to generate an output signal at the second output side corresponding to data stored in the cell.

Abstract: An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

Abstract: A standard SNMP management station is replaced by a client computer having a standard Web browser while utilizing the services of a Web/SNMP proxy agent in accordance with the present invention. The Internet locations of the ASN.1 specifications for various MIB modules, as well as other information resources associated with those MIB modules, are stored in resource records in a section of the DNS established for storing such information. The Web/SNMP proxy agent automatically locates the ASN.1 specification for each MIB module of any identified SNMP agent, by looking up the location in the DNS. The Web/SNMP proxy agent then compiles the ASN.1 MIB module specifications into HTML documents for viewing on the client computer. User requests for retrieving data from specified MIB objects and/or for sending data values to specified MIB objects are communicated from the client computer to the Web/SNMP proxy agent using standard HTTUP communications.

Abstract: A low power, low noise driving circuit for a bank of LEDs utilized in the station units of the MAN system is provided by coupling each bank of LEDs in a series circuit between the voltage supply and a constant current source. Each LED has a controllable logic switch in parallel across it and the switches are further in series circuit with each other to form a ladder network. Any selected LED may be turned off by closing its corresponding logic switch. The current continues to flow then through the shunting switch into the remaining LEDs in the series circuit that are on. A plurality of such ladder networks may be coupled in parallel with each other and each ladder network controlled by a switching gate which selectively couples it to the constant current source so that the LED ladder networks are operated at a predetermined duty cycle.

Abstract: A method for reading data in a data reading and writing system is disclosed. The method can effectively shorten the data-reading cycle.

Abstract: Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.