Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Abstract: Logic may support full power operation for uplink transmissions of user equipment. Logic may identify a codebook entry with a precoding matrix for full power mode operation for an uplink communication for a set of non-coherent or partial coherent antenna ports. Logic may generate the uplink communication, generation to comprise precoding one or more data streams of the uplink communication based on the precoding matrix to associate the data streams with the set of non-coherent or partial coherent antenna ports. And logic may cause transmission of the uplink communication via the interface between processing circuitry and radio frequency circuitry.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to control transactional data. An example apparatus disclosed herein includes memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to populate encrypted input data into a first portion of a data structure, populate an encryption key into a second portion of the data structure, cause the first portion of the data structure to be signed with (a) credentials corresponding to an owner of the encrypted data and (b) credentials corresponding to a transaction host, and store the data structure in a ledger.

Abstract: Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.

Abstract: Methods, apparatus, systems are disclosed for altering displayed content on a display device responsive to a user's proximity. In accord with an example, a computing system includes a display, a sensor to output a signal, machine readable instructions, and programmable circuitry to be programmed in accordance with the instructions to determine a distance between the compute system and a person based on the signal, and cause a size of at least one object to be presented on the display to be adjusted based on the distance.

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.

Abstract: Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.

Abstract: A virtual machine (VM) management utility tool may deploy an object model that may persist one or more virtual machine dependencies and relationships. Through a web front-end interface, for example, the VMs may be started in a specific order or re-booted, and the tool automatically determines the additional VMs that need to be re-booted in order to maintain the integrity of the environment. Through the web interface, for example, the object model may be managed and start-up orders or VM dependencies may be updated. For VMs that may not start under load, the object model may block access to the VM until the VM is fully initialized.

Abstract: Systems and methods are provided for harmonizing a foreground region with a background image during background replacement and content editing. A sensor image including a foreground region and a background region is received at an image signal processor (ISP), along with a background image having different visual characteristics. The sensor image and the background image are downscaled and processed by a harmonization neural network that predicts one or more ISP hardware block parameters. The predicted parameters are used to configure ISP hardware blocks such that the foreground region of a processed image is harmonized to match visual characteristics of the background image while preserving full sensor bit depth. The processed image is then blended with the background image to generate a harmonized output image.

Abstract: An apparatus, system, and method for multi-frequency oscillator control are provided. A circuit can include a resonator circuit including an input and an output, the resonator circuit configured to resonate at a fundamental frequency and a different, non-fundamental frequency, a startup circuit electrically coupled to the input, the startup circuit configured to generate a signal at about the non-fundamental frequency and detect when the resonator circuit is resonating at the non-fundamental frequency, and an oscillator driver circuit electrically coupled to the output, the oscillator driver circuit configured to amplify and buffer the output of resonator circuit and drive a load.

Abstract: An apparatus can include radio-frequency transceiver circuitry to transmit and receive radio-frequency signals in a first communications band and in a second communications band. The apparatus can further include a diplexer coupled to the radio-frequency transceiver circuitry. The diplexer can have terminals connected to a first path that conveys the radio-frequency signals in the first communications band and a second path that conveys the radio-frequency signals in the second communications band. The diplexer terminals can also connect to a first switch interposed in the first path and a second switch interposed in the second path.

Abstract: A station (STA) (STA-1) configured for wireless local area network (WLAN) sensing establishes a sensing measurement agreement with another STA STA-2 to perform a sensing measurement setup with the other STA. The sensing measurement setup may comprise an exchange of sensing measurement request and response frames to establish sensing measurement parameters associated with a sensing measurement instance. The Sensing Measurement Setup Request frame and the Sensing Measurement Setup Response frame may be configurable to include a variable length Measurement Sensing Parameters field and a sensing sub-elements field to include one or more of the sensing measurement parameters. The sensing measurement parameters may, for example, comprise one or more of a bandwidth (BW) field, one or more fields for a number of space-time streams (STS) and a number of long-training field (LTF) and LTF repetitions that the STA is capable of transmitting and receiving, and an immediate or delayed feedback reporting field.

Abstract: Circuit apparatus are disclosed. An example circuit apparatus includes a body including a plurality of first traces formed on the body, and a plurality of openings formed through the body and located between respective ones of the first traces. The openings provide airflow to a fan module of an electronic device through the body of the circuit apparatus.

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

Abstract: Embodiments are generally directed to sparse 3D convolution acceleration in a convolutional layer of an artificial neural network model. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including feature maps. The one or more processors are to provide for sparse 3D convolution acceleration by applying a shared 3D convolutional kernel/filter to an input feature map to produce an output feature map, including increasing sparsity of the input feature map by partitioning it into multiple disjoint input groups; generation of multiple disjoint output groups corresponding to the input groups by performing a convolution calculation represented by the shared 3D convolutional kernel/filter on all feature values associated with active/valid voxels of each input group to produce corresponding feature values within corresponding output groups; and outputting the output feature map by sequentially stacking the output groups.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip package assembly having a spring element to be coupled between a first mechanical element and a second mechanical element to apply a loading force that pulls the first and second mechanical elements toward each other in the assembly's nominal assembled state. The first and second elements to support a cooling mass, the assembly further comprising a dampener that is coupled to at least one of the first and second mechanical elements to reduce oscillation amplitude of the cooling mass.

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.