Abstract: This disclosure describes systems, methods, and devices related to decoding low-complexity enhancement video coding (LCEVC) video data. A device may receive a bitstream including a first layer and enhancement layers; decode a video frame of the first layer of the bitstream using a base decoder; up-sample the decoded video frame; decode the video frame of a first enhancement layer using tile-level quantization parameters; generate a first combined intermediate video frame using the up-sampled video frame and the decoded video data of the first enhancement layer; up-sample the first combined intermediate video frame; decode encoded video data of a second enhancement layer; generate a second combined intermediate video frame using the decoded video data of the second enhancement layer and a selected reference frame; and generate a combined output video frame using the first combined intermediate video frame and the second combined intermediate video frame.

Abstract: Via structures for hybrid bonding architectures, and methods for making same. The structures include a die with a plurality of conductive contacts arranged at a pitch of less than about 4 microns in a hybrid bonding interface. The first layer of metal is below the plurality of conductive contacts, and a second layer of metal is below the first layer of metal and separated therefrom by an insulating layer. A via structure in the die comprises copper or tungsten and is electrically coupled at a first end to a first conductive contact of the plurality of conductive contacts and electrically coupled at a second end to the second layer of metal. A second conductive contact located sequentially next to the first conductive contact is electrically coupled to the first layer of metal.

Abstract: Disclosed is a technical solution to generate hardware-aware machine learning (ML) model architectures for multiple domains without training. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions. The example processor circuitry is to generate multiple candidate architectures for a ML model based on target hardware with which the ML model is to be executed and a search space corresponding to the multiple domains. Additionally, the example processor circuitry is to compute respective composite scores for the multiple candidate architectures, the respective composite scores based on respective latency scores for the multiple candidate architectures.

Abstract: Hardware accelerator designs for neural networks are improved with various approaches to reduce circuit area, improve power consumption, and reduce starvation. Convolutional layers of a neural network may multiply a set of weights with a set of inputs. One example defers two’s complement arithmetic from the parallelized multiplication circuits and completes the two’s complement arithmetic when the results are accumulated. In another example, a multiplication circuit initially multiplies an input by an initial value of the maximum (or minimum) multiplication range before applying the magnitude of a multiplication encoded relative to the multiplication range. In another example, after dimensional reduction earlier in the network hardware, circuitry for a convolutional layer uses a reduced number of convolutional block circuits that are reused across a plurality of clock cycles to apply different subsets of weight channels.

Abstract: Devices and systems with stacked memory, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a logic die, a stack of memory dies above the logic die, and a passthrough die between the logic die and the stack of memory dies, where the logic die is conductively coupled to the stack of memory dies through the passthrough die.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: Embodiments are generally directed to dynamically dividing activations and kernels for improving memory efficiency. An embodiment of a method in a compute engine performing machine learning comprises: receiving, by a convolutional layer of a convolutional neural network (CNN) implemented on the compute engine, a plurality of activation groups contained in an input data, wherein the convolutional layer includes one or more kernel groups and the one or more kernel groups each include a plurality of kernels; determining a plurality of memory efficiency metrics based on the number of activation groups of the plurality of activation groups and the number of kernels of the plurality of kernels; selecting a first optimal number of activation groups and a second optimal number of kernels that are associated with an optimal memory efficiency metric in the plurality of memory efficiency metrics; and performing a convolutional operation on the input data based on the first optimal number and the second optimal number.

Abstract: A system is provided that includes a set of graph processing cores and a set of dense compute cores, where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications, the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: An apparatus and system of paging using paging early indication (PEI) and subgrouping are described. A fifth generation nodeB (gNB) checks paging information of a UE from a limited paging container of the UE provided from the core network to determine whether PEI/subgrouping information is present. The limited paging container contains paging information of the UE that is provided in the UE capability and is used by a previous gNB. If the paging information of the UE does not indicate the ability of the UE to use PEI and/or subgrouping, the gNB checks the information in the UE capability; if the paging information and the UE capability conflict, the gNB signals the UE to monitor for PEI/Subgrouping. The gNB updates the paging capability with PEI and/or subgrouping support before the UE enters idle mode or inactive state and sends the update to the core network.

Abstract: Methods and apparatus for two-layer Alpha-based buffer management with dynamic RED. A two-layer hierarchical sharing scheme using alpha parameters is provided. A buffer is dynamically shared across upper-level entities, such as hosts, using one set of alpha parameters, then a dynamically-adjusted buffer portion allocated for an upper level entity is shared among its lower level entities (e.g., sub queues) using a separate set of low-level alpha parameters. The memory spaces for the upper- and lower-level entities may be dynamically redistributed. Determinations to drop and/or mark and ECN field of received packets are performed using Dynamic RED, which employs dynamic thresholds and associated dynamic probabilities.

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.

Abstract: A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.

Abstract: Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Abstract: Predictive Failure Analysis (PFA) techniques that are thermal aware can enable the prevention of uncorrectable errors without premature replacement of memory resources with redundant memory resources. In one example, a management controller (such as Baseboard Management Controller (BMC)) can monitor the rate of corrected errors. When the BMC detects that there are too many corrected errors occurring within certain time duration, the BMC can check the temperature and airflow rate of memory modules. Based on temperature data, the BMC can boost the fans and verify the reduction in memory corrected errors. If after multiple retries the rate of corrected error remains same, the BMC can enable memory resource replacement techniques such as SDDC or ADDDC or sparing on the failing memory module.

Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Abstract: Systems, apparatuses and methods may provide for technology that determines a selected priority corresponding to a selected region in a microprocessor, determines an adjacent priority corresponding to an adjacent region in the microprocessor, wherein the adjacent region is adjacent to the selected region, and places the adjacent region in a first reduced power state if the selected priority is greater than the adjacent priority and temperature of the selected region is less than a selected temperature threshold associated with the selected region.

Abstract: Systems, methods, and apparatuses for implementing capability-directed array prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory; a capability management circuit to check a capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.

Abstract: Examples relate to a concept for providing access to remote memory. A network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. The circuitry is configured to translate the memory transaction request to a cache transaction request. The circuitry is configured to provide the cache transaction request to the first host. The circuitry is configured to obtain a response to the cache transaction request from the first host. The circuitry is configured to provide information on the response to the cache transaction request to the second host.