Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a chassis, where the chassis includes a first chassis portion and a second chassis portion, a flexible display supported by the chassis, and a hinge. The hinge includes a first chassis attachment housing coupled to the first chassis portion, a first chassis portion lift arm coupled to the first chassis attachment housing, a first hinge pivot coupled to the first chassis portion lift arm, a second chassis attachment housing coupled to the second chassis portion, a second chassis portion lift arm coupled to the second chassis attachment housing, and a second hinge pivot coupled to the second chassis portion lift arm.

Abstract: Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.

Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.

Abstract: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.

Abstract: In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.

Abstract: Write filter hardware is provided with circuitry to receive a signal to switch the write filter from a disabled state to an enabled state for a given range of addresses in a shared memory. A write attempt by a host processor to the range of addresses is identified, where access to the shared memory is shared with an accelerator device. The write filter hardware causes the write attempt to be dropped when the hardware write filter is in the enabled state for the given range of addresses.

Abstract: A method and system of neural network dynamic noise suppression (DNS) is provided for audio processing. The system is a down-scaled DNS model that uses grouping techniques at pointwise convolutional layers to reduce the number of network parameters. According to one technique, audio signal data can be coded into an input vector that that is split into multiple groups, each groups having multiple channels. At a pointwise convolution layer, an output is generated for each group. The outputs can be concatenated to form a single input vector for a next layer of the model. Each group is treated as a channel, such that the reduction in the number of channels reduces the number of parameters used by the neural network. In some examples, the groups are weight sharing groups.

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.

Abstract: Voice anonymization systems and methods are provided. Voice anonymization is done on the speaker's computing device and can prevent voice theft. The voice anonymization systems and methods are lightweight and run efficiently in real time on a computing device, allowing for speaker anonymity without diminishing system performance during a teleconference or VoIP meeting. The anonymization system outputs a transformed speaker voice. The anonymization system can also generate a voice embedding that can be used to reconstruct the original speaker voice. The voice embedding can be encrypted and transmitted to another device. Sometimes, the voice embedding is not transmitted and the listener receives the anonymized voice. Systems and methods are provided for the detection of voice transformations in received audio. Thus, a listener can be informed whether the speaker voice output from the listener's computing device is the original speaker's voice or a transformed version of the original speaker voice.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. The example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.

Abstract: Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, KVCrush, which stands for KEY-VALUE CACHE SIZE REDUCTION USING SIMILARITY IN HEAD-BEHAVIOR, is implemented. KVCrush involves using binary vectors to represent tokens, where the vector indicates which attention heads attend to the token and which attention heads disregard the token. The binary vectors are used in a hardware-efficient, low-overhead process to produce representatives for unimportant tokens to be pruned, without having to implement k-means clustering techniques.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for high quality and low power dynamic region of interest (ROI) cropping. An example apparatus disclosed herein provides a first image to image signal processor (ISP) circuitry, the ISP circuitry to implement an image processing pipeline to process the first image. The example apparatus also downscales the first image to generate a second image having lower resolution than the first image and identifies a region of interest (ROI) in the second image. The example apparatus further provides coordinates of the ROI to the ISP circuitry, the ISP circuitry to crop the first image based on the coordinates and to output a third image based on the cropped first image.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to map workloads. An example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to dynamically manage input/output (I/O) transactions. An example apparatus includes circuitry to determine at least one of a first parameter assigned to an VO transaction by a user, a second parameter for the I/O transaction based on at least a class of an I/O device, or a third parameter for the I/O transaction based on a usage pattern for a compute device coupled to the I/O device. Additionally, the example apparatus includes parameter management circuitry to determine a dynamic parameter to assign to the I/O transaction based on at least one of the first parameter, the second parameter, or the third parameter and cause scheduler circuitry to at least one of adjust a default bandwidth to be allocated to the I/O transaction based on the dynamic parameter or adjust a latency associated with the I/O transaction based on the dynamic parameter.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to estimate a pose of a head of a user of an electronic device. An example apparatus to estimate a head pose includes at least one processor circuit to be programmed by instructions to: identify a plurality of facial landmarks in a plurality of images; identify initial image data based on the plurality of facial landmarks; augment the initial image data with a transformation operation; and train a neural network based on the initial image data and the augmented image data to: infer three-dimensional model parameters; and infer a confidence metric.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to utilize large language artificial intelligence models to convert computer code. An example apparatus includes instructions and processor circuitry to execute the instructions to at least: train a large language model based on a computer instructions repository that includes code of a first type; utilize the large language model to convert an input set of instructions of the first type into output code of a second type; cause execution of the output code; determine if the execution is successful; and when the execution is not successful, utilize the output code for fine-tuning training of the large language model with incorrect data.

Abstract: Systems, apparatus, articles of manufacture, and methods to save power during conference calls are disclosed. An example first client device includes interface circuitry; machine readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine readable instructions to: determine whether a first attendee of a conference call is absent from the first client device; and cause transmission of a notification to at least one of a server for the conference call or a second client device associated with the conference call and different from the first client device, the notification to cause the second client device to change an operating state associates with the conference call.