Patents Assigned to Intel Corporation
  • Patent number: 11025627
    Abstract: Various systems and methods of scalable and secure resource isolation and sharing for Internet of Things (IoT) networks, are described. Techniques for requesting inter-domain resource access and enabling resource sharing with use of an inter domain token are also described. In an example, communications in an IoT network to establish connectivity between a first device in a first domain and a second device in a second domain may include: receiving, from the first device at a collaboration cloud service, a request to access a resource of the second device; requesting and receiving, from an authorization provider, an inter-domain authorization token; and requesting, from the second device, access to the resource using the inter-domain authorization token; communications from the first device to access the second device are then performed between the first device and the second device based on a session key obtained with the inter-domain authorization token.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Weigang Li, Ned M. Smith, Changzheng Wei
  • Patent number: 11025719
    Abstract: Multiple devices are detected in an environment and a user input is received to define a relationship between two or more devices in the plurality of devices. A system can determine that a first of the two or more devices includes a sensor resource and a second of the two or more devices includes an actuator resource. Data is identified describing outputs of the first device corresponding to the sensor resource and inputs of the second device corresponding to the actuator resource. A model is generated modeling interoperation of the sensor resource and actuator resource based at least in part on the data.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Shao-Wen Yang, Yen-Kuang Chen, Nyuk Kin Koo
  • Patent number: 11025804
    Abstract: An example apparatus for generating panoramic video includes a number of modular wedges. Each of the modular wedges also includes two high resolution imaging sensors. Each of the modular wedges further includes two discrete lenses coupled to one side of the modular wedge. Each of the modular wedges also further includes two transceivers coupled to the imaging sensors to output video data.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Nathan Stebor
  • Patent number: 11024007
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Patent number: 11026351
    Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a closed cooling loop thermally coupled to one or more processors disposed on a circuit board of the computing apparatus. The closed cooling loop circulates a dielectric fluid to absorb heat from the processor. A portion of the dielectric fluid is evaporated from the processor heat absorbed by the dielectric fluid. A heat exchanger is coupled to the circuit board and thermally coupled to the closed cooling loop. The heat exchanger is to include a coolant flow to remove heat from the dielectric fluid circulated through the portion of the closed cooling loop thermally coupled to the heat exchanger. A vapor portion of the dielectric fluid is condensed from the heat removed by the coolant flow. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Richard J. Dischler
  • Patent number: 11023235
    Abstract: Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine, Mark J. Charney, Bret Toll, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Menachem Adelman, Eyal Hadas
  • Patent number: 11023067
    Abstract: A device may be controlled using a fingerprint input. Data indicative of a fingerprint is received from a sensor. It is determined that the fingerprint is associated with a first finger profile that is usable to distinguish a first finger from other fingers of a user of the device. A user control that is associated with the finger profile is identified. The user control is configured to control a setting of a function executing on the device. The user control is input to control the first setting.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Tim Schoenauer, Bernhard Raaf
  • Patent number: 11023382
    Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Jason Brandt, Mark J. Charney, Joseph Nuzman, Leena Puthiyedath, Rinat Rappoport, Vivekananthan Sanjeepan, Robert Valentine
  • Patent number: 11024574
    Abstract: Described is an apparatus which comprises: a die with a first side; a first set of solder balls coupled to the die along the first side; a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having at least one balun, at least one bandpass filter (BPF), and at least one diplexer embedded in the laminate, wherein the at least one balun is communicatively coupled to the first die via at least one of the solder balls of the first set.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Sidharth Dalmia
  • Patent number: 11025520
    Abstract: Systems and techniques for quality-of-service (QoS) in cellular information centric network (ICN) are described herein. To this end, QoS characteristics may be obtained for an ICN packet. The QoS characteristics may then be applied to the ICN packet. The ICN packet may then be transmitted in accordance with the QoS characteristics.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 1, 2021
    Assignee: INTEL CORPORATION
    Inventors: Yi Zhang, Zongrui Ding, S. M. Iftekharul Alam, Satish Chandra Jha, Gabriel Arrobo Vidal, Kuilin Clark Chen
  • Patent number: 11023803
    Abstract: One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: June 1, 2021
    Assignee: INTEL CORPORATION
    Inventors: Dhiraj D. Kalamkar, Karthikeyan Vaidyanathan, Srinivas Sridharan, Dipankar Das
  • Patent number: 11024041
    Abstract: A mechanism is described for facilitating depth and motion estimation in machine learning environments, according to one embodiment. A method of embodiments, as described herein, includes receiving a frame associated with a scene captured by one or more cameras of a computing device; processing the frame using a deep recurrent neural network architecture, wherein processing includes simultaneously predicating values associated with multiple loss functions corresponding to the frame; and estimating depth and motion based the predicted values.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 1, 2021
    Assignee: INTEL CORPORATION
    Inventors: Koba Natroshvili, Kay-Ulrich Scholl
  • Patent number: 11023824
    Abstract: Methods, apparatus, and machine-readable mediums are described for selecting a training set from a larger data set. Samples are divided into a training set and a validation set. Each set meets one or more conditions. For each class to be modeled, multiple training sets are created. Models are trained on each of the multiple training sets. A size of samples for each class is determined based upon the trained models. A training data set that includes a number of samples based upon the determined size of samples is created.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Luis Sergio Kida
  • Patent number: 11024094
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to map a virtual environment to a physical environment using a weighted linear mapping technique. Example methods disclosed herein include accessing dimensional data corresponding to the virtual environment. Disclosed example methods further include determining areas of relative importance in the virtual environment. Disclosed example methods also include accessing dimensional data corresponding to the physical environment and generating a mapped environment based on the dimensional data corresponding to the virtual environment, the dimensional data corresponding to the physical environment, and the areas of relative importance.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Chao Huang, Zhen Zhou, Manuj Sabharwal
  • Patent number: 11023998
    Abstract: An apparatus is provided which comprises: a first engine buffer to receive a first engine request; a first engine register coupled to the first engine buffer, wherein the first engine register is to store first engine credits associated with the first engine buffer; a second engine buffer to receive a second engine request; a second engine register coupled to the second engine buffer, wherein the second engine register is to store second engine credits associated with the second engine buffer; and a common buffer which is common to the first and second engines, wherein the first engine credits represents one or more slots in the common buffer for servicing the first engine request for access to a common resource, and wherein the second engine credits represents one or more slots in the common buffer for servicing the second engine request for access to the common resource.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Nicolas Kacevas, Niranjan L. Cooray, Madhura Joshi, Satyanarayana Nekkalapu
  • Patent number: 11019864
    Abstract: A smart fabric may include a smart material such as an Electroactive Polymer (EAP). An adaptive garment formed from the smart fabric may change textile density based on user needs, sensor states, context, and other inputs. In various embodiments, the EAP enables the adaptive garment to change textile density based on a sport or activity, based on calendar or scheduled events, or based on user preferences. In various embodiments, these smart fabrics may be implemented in sporting garments, uniforms, multiple-day clothing (e.g., for travel or military usage), furniture fabric, curtains, or other implementations.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Tomer Rider, Shahar Taite
  • Patent number: 11024002
    Abstract: An example apparatus for correcting gaze in images includes an image receiver to receive an image comprising an eye and a target angle set to a center. The apparatus also includes a bidirectionally trained convolutional neural network (CNN) to receive the image and the target angle from the image receiver and generate a vector field and a brightness map based on the image and the target angle. The apparatus further includes an image corrector to generate a gaze corrected image based on the vector field and the brightness map.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Furkan Isikdogan, Timo Gerasimow, Gilad Michael
  • Patent number: 11024601
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
  • Patent number: 11024356
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Patent number: 11024713
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani