Patents Assigned to Intel Corporation
  • Patent number: 11921632
    Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian, Fengguang Wu, Jingqi Liu
  • Patent number: 11921635
    Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventor: Altug Koker
  • Patent number: 11922178
    Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Arnab Raha, Deepak Mathaikutty, Debabrata Mohapatra, Sang Kyun Kim, Gautham Chinya, Cormac Brick
  • Patent number: 11921652
    Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Amit Kumar Srivastava, George Vergis
  • Patent number: 11921645
    Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Prashant Dewan, Abhishek Basak, David M. Durham
  • Patent number: 11923257
    Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
  • Patent number: 11921646
    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: David Koufaty, Rajesh Sankaran, Anna Trikalinou, Rupin Vakharwala
  • Patent number: 11923268
    Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington
  • Patent number: 11922227
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith
  • Patent number: 11923410
    Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
  • Patent number: 11922220
    Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
  • Patent number: 11924676
    Abstract: Embodiments herein provide methods of sidelink communication between nodes including resource selection, congestion control, and/or resource signaling. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Mikhail Shilov, Alexey Khoryaev, Sergey Panteleev, Sergey Sosnin, Kilian Roth
  • Patent number: 11922274
    Abstract: Quantum dot devices with three of more accumulation gates provided over a single row of a quantum dot formation region are disclosed. Each accumulation gate is electrically coupled to a respective doped region. In this manner, multiple single electron transistors (SETs) are provided along the row. Side and/or center screening gates may be used to apply microwave pulses for qubit control and to control electrostatics so that source and drain regions of the multiple SETs with quantum dots formed along the single row of a quantum dot formation region are sufficiently isolated from one another. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Hubert C. George, James S. Clarke, Ravi Pillarisetty, Brennen Karl Mueller, Stephanie A. Bojarski, Eric M. Henry, Roza Kotlyar, Thomas Francis Watson, Lester Lampert, Samuel Frederick Neyens
  • Patent number: 11924923
    Abstract: An access point (AP) configured for wireless local area network (WLAN) sensing is configured to encode a trigger frame (TF) for transmission. The trigger frame allocates resource units (RUs) for receiving high-efficiency (HE) trigger-based (TB) physical-layer protocol data units (PPDUs) (HE TB PPDUs) from a plurality of client devices (non-AP STAs). The trigger frame may solicit each of the client devices to transmit an HE TB PPDU in accordance with an UL OFDMA technique or an UL MU-MIMO technique. The AP may decode the HE TB PPDUs received from the client devices and may estimate channel state information (CSI) for a radio link associated with each of the client devices based on an HE-LTF of an associated one of the HE-TB PPDUs received from one of the client devices. In accordance with these embodiments, the AP may process changes in the CSI of the radio links over time for a WLAN sensing application.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bahareh Sadeghi, Carlos Cordeiro, Claudio Da Silva, Cheng Chen
  • Patent number: 11921871
    Abstract: Systems, apparatuses and methods may provide for detecting an identifier communication from a writing implement and transitioning a previously modified interior page of an electronic notepad from a locked state to an unlocked state if the identifier communication corresponds to one or more stored identifiers. Moreover, a plurality of additional interior pages of the electronic notepad may be maintained in the locked state while the previously modified interior page is in the unlocked state.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Arvind Kumar, James M. Okuley
  • Patent number: 11924866
    Abstract: Embodiments of an Extremely High Throughput Station (EHT STA) (STA1) configured for operating in a next-generation (NG) wireless local area network (WLAN) are described herein. In some embodiments, the EHT STA encodes a common signal field (SIG) (Coex-SIG) of an EHT PPDU to include a TXOP duration field. The TXOP duration field is more than seven bits to indicate an actual TXOP duration of a transmission from the EHT STA comprising the EHT PPDU transmitted to a second station (STA2). Decoding the TXOP duration field of the EHT PPDU by a third-party station (STA4) causes the third-party station (STA4) to defer a transmission until after an end of the transmission from the second station (STA2).
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Thomas J. Kenney, Laurent Cariou, Po-Kai Huang, Qinghua Li, Xiaogang Chen, Feng Jiang
  • Patent number: 11921473
    Abstract: Apparatus, systems, articles of manufacture, and methods to generate acceptability criteria for autonomous systems plans are disclosed. An example apparatus includes a data compiler to compile data generated by the autonomous system into an autonomous system task dataset, a data encoder to encode the dataset for input into a rule distillation neural network architecture, a model trainer to train the rule distillation neural network architecture, an adaptor to adapt the trained rule distillation neural network architecture to a new input data domain using the autonomous system task dataset, a verifier to generate formally verified acceptability criteria, and an inferer to evaluate a control command, the evaluation resulting in an acceptance or rejection of the command.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 5, 2024
    Assignee: INTEL CORPORATION
    Inventors: Javier Felip Leon, Javier Sebastian Turek, David I. Gonzalez Aguirre, Ignacio Javier Alvarez, Luis Carlos Maria Remis, Justin Gottschlich
  • Patent number: 11923307
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
  • Patent number: 11922152
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify workload control variables, add workload flags to respective edges in a static single assignment graph, and propagate constants based on the identified workload control variables and the workload flags. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventor: Yuan Chen
  • Patent number: 11923290
    Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson