Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: A method for resolving ambiguities in user input to a computer-aided drawing package. The number of necessary commands is therefore reduced. To draw an element, the user selects a particular drawing command. The user then manipulates a pointing device to select points that further define the position and shape. In accordance with the invention, the point selections can be interpreted in more than one way. A region surrounding at least one of the selected points is divided into so-called intent zones. After, this point is selected, the drawing package monitors cursor movement through this region. The particular intent zone that the cursor traverses determines the interpretation of the point selections following the command.

Abstract: A method for maintaining relationships between entities in a computer system, each entity having a plurality nodes, includes the steps of: modifying one of the plurality of nodes; searching for a plurality of dependent nodes from the plurality of nodes coupled to the one node; ordering the plurality of dependent nodes into an order; and evaluating the plurality of dependent nodes in the order.

Abstract: An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the input virtual address. If they match, then the requested data resides in the intermediate storage device, and an instruction issuing unit allows the instructions to continue issuing to an instruction pipeline as scheduled. However, if the virtual address tag does not match the relevant portion of the input virtual address, then it is assumed that a page fault might occur, and the instruction issuing unit inhibits the issuance of further instructions to the instruction pipeline.

Abstract: An apparatus and method for allocating, linking and using blocks of memory to represent a data object in an object-oriented programming environment, particularly COM programming environments. The invention eliminates the conventional viable pointers, reference counters, controlling unknown pointers and other infrastructure overhead from the data objects. This information is instead allocated on a temporary basis only while an object is in use, in object and interface wrappers.

Abstract: An internal component within the interior of a computer chassis is accessible via a chassis door that may be moved into the chassis interior. To that end, the chassis includes a housing defining the interior that contains the internal component, and the door, which is movably coupled to the housing. The housing also includes a front face that forms an access port to the internal component within the interior. The door may be alternatively moved to an open position and a closed position. When in the closed position, the door substantially covers the access port to prevent access to the internal component. When in the open position, the door is within the housing interior, thus exposing the internal component to the access port.

Abstract: An apparatus and method of applying an effect to graphical data utilizes a graphics processor to apply the effect to a graphical image having the graphical data. To that end, the graphics processor is configured to process graphical data in accordance with a preselected graphics processing format, and the effect and graphical image are defined and converted, respectively, into the preselected graphics processing format. The graphics processor is controlled to apply the effect to the graphical image to produce an output graphical image. The output graphical image includes both the effect and the graphical image. The graphics processor may be a graphics accelerator card, and the graphics processing format may be the OPENGL™ application program interface.

Abstract: A method for manipulating a first three-dimensional object, in a computer system including a display, a first software application, and a second software application. The present method includes the step of creating a model of the first three-dimensional object with the first software application, which has a first three-dimensional object with the first system. A step of storing the model of the first three-dimensional object in a model format is also included. The present method further includes the step retrieving the model of the first three-dimensional object in the model format into a second software application, the second software application having a second coordinate system. The present method also includes the step of manipulating a view of the model of the first three-dimensional object with the second software application and within the second coordinate system.

Abstract: An apparatus and method are described for implementing handling of exceptions caused by speculated instructions in a CPU having speculative execution capabilities. A CPU implementing speculative execution contains a speculative bit register file. Each speculative bit in the speculative bit register file is logically associated with a particular general purpose register, while remaining physically separate. This is accomplished through the use of a physically separate register file (the speculative bit register file) and register selection circuitry allowing simultaneous access to the two register files. The present invention provides instruction execution hardware supporting speculative execution with minimal impact on computational and structural complexity.

Abstract: A system for detecting and reporting memory errors in error correctable memory in a computer system includes a chipset that utilizes the error correctable memory for creating an error detection signal when a memory error occurs. The error detection signal includes data that may be utilized to identify the error correctable memory having a memory error. The system further includes a motherboard having two or more memory interface slots, where the error correctable memory is coupled with at least one of the interface slots, and each of the at least one slots has a unique slot identification number. The chipset is coupled to the motherboard, and the system further includes a driver coupled to the chipset. The motherboard has at least one register that receives the error detection signal and stores the data in the error detection signal in the at least one register.

Abstract: An apparatus for and method of directing graphical data toward a display device from a plurality of graphics processors couples the graphics processors in a manner that reduces the size of the interface on each graphics processor. In particular, each graphics processor produces graphical data for an associated set of pixels on the display device, where each pixel is represented by a first amount of graphical data. The graphics processors are arranged so that one of the graphics processors is a destination processor. The total number of graphics processors that are not designated as the destination processor thus constitute a remaining number. Each graphics processor produces a second amount of graphical data during each clock cycle of a common clock. The first amount of graphical data, however, is comprised of at least substantially two times the second amount of graphical data.

Abstract: A computer system with an improved graphically-oriented user interface that permits the user to more easily select for manipulation one object from a number of objects that overlap or are in close proximity to one another at a common location in a graphic display. In a preferred embodiment, the invention presents the computer user with the opportunity to preview all possible objects that the cursor might be identifying at its current position and the ability to select one of those objects for manipulation. Thus, rather than cycling through the entire list of objects available for selection at a location in the display, the user can immediately narrow the list down to the desired selection only. The present invention prevents selection errors and drastically reduces the number of user inputs required to select an object.

Abstract: A method for maintaining relationships between entities in a computer system, each entity having a plurality nodes, includes the steps of: modifying one of the plurality of nodes; searching for a plurality of dependent nodes from the plurality of nodes coupled to the one node; ordering the plurality of dependent nodes into an order; and evaluating the plurality of dependent nodes in the order.

Abstract: A method of synchronizing, at a system frame display rate, a first set of frames displayed by a first monitor with a second set of frames by a second monitor, utilizes frame production rates of the two sets of frames to set the system frame display rate. More particularly, the first set of frames are produced at a first frame production rate by a first graphics engine, and the second set of frames are produced at a second frame production rate by a second graphics engine. The first frame production rate and second frame production rate first are compared to determine which frame production rate is slower. The system frame display rate then is set to be no greater than the slower of the two frame production rates.

Abstract: A graphics accelerator includes a plurality of digital signal processors that are arranged in a self-regulating, peer-to-peer configuration. Accordingly, the processors cooperate to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. To that end, each processor includes a request bus, an input in communication with the request bus, and an output coupled to a sequencer for ordering graphics requests processed by the digital signal processors.

Abstract: A method, apparatus, and computer program product for accessing random access memory (RAM) in a computer system running a virtual memory operating system designates a part of the RAM as system memory for use by the operating system. This memory designation consequently produces a remainder memory in the RAM. The remainder memory may be directly accessed by a virtual memory manager upon receipt of an access message requesting access to the remainder memory. The virtual memory manager is controlled to bypass its nonpaged pool controller when accessing the remainder memory. Bypassing the nonpaged pool controller significantly enlarges the available RAM that may be used for temporarily storing data files.

Abstract: A method, apparatus, and computer program product for testing a computer system having a set of computer components and a testing program stored in memory provides both a test header file associated with a selected component, and a component file listing the set of components of the computer system. The test header file and component header file are compared to determine if the selected computer component is one of the set of components of the computer system. If it is determined that the selected component is one of the set of components of the computer system, then the testing program is executed.

Abstract: An apparatus and method for allocating, linking and using blocks of memory to represent a data object in an object-oriented programming environment, particularly COM programming environments. The invention eliminates the conventional viable pointers, reference counters, controlling unknown pointers and other infrastructure overhead from the data objects. This information is instead allocated on a temporary basis only while an object is in use, in object and interface wrappers.

Abstract: A method for positioning a cursor relative to a reference position on the display using the pointing device includes the steps of positioning the cursor at a position on a display with a pointing device, selecting the position as the reference position, the reference position associated with an object, moving the cursor to a plurality of cursor positions not associated with the object on the display with the pointing device, and displaying a plurality of offset values on the display, the offset values being calculated in response to the reference position and the plurality of cursor positions.

Abstract: An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the input virtual address. If they match, then the requested data resides in the intermediate storage device, and an instruction issuing unit allows the instructions to continue issuing to an instruction pipeline as scheduled. However, if the virtual address tag does not match the relevant portion of the input virtual address, then it is assumed that a page fault might occur, and the instruction issuing unit inhibits the issuance of further instructions to the instruction pipeline.