Abstract: An apparatus for stiffening a circuit board during soldering, assembly, and repair/rework, which includes an elongated crossmember having two opposing ends, an outer support leg extending downward from each crossmember end to form a bridge support with the crossmember and a central support leg extending downward from a central portion of the crossmember. A central portion of the circuit board is attached to the central support member to prevent the circuit board from softening and sagging when exposed to the heat from soldering.

Abstract: A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags.

Abstract: A system for efficiently generating on a raster line plotter an image that is made up of a plurality of characters, or other objects, based on an opaque ink model. Information relating to the characters is run length encoded, so as to form tone run records corresponding to the raster lines. The tone run records contain information relating to tone value, starting location, length and screen selection. The information is then processed so as to delete, or overwrite, tone value and screen selection information of the portions of characters that underlie other characters. After the appropriate information has been deleted, the remaining screen selection and tone value information is used to create a halftone image.

Abstract: A method of simulating the operation of a circuit utilizing voltage or current data obtained from measurements of actual samples of each of the circuit components. The actually measured voltage or current data is employed to mathematically analyze operation of the circuit. In this process, each circuit component is characterized as one or more of a voltage controlled voltage source, voltage controlled current source, current controlled voltage source and current controlled current source. After such characterization, a trial operating point is selected and values of current or voltage between actually measured data points are determined and linearized circuit equations are established with spline equations. The linearized equations are solved. The steps are repeated with a new trial operating point in accordance with a Newton-Rhapson iterative technique until the solution of the linearized equations is within a predetermined range.

Abstract: A system for scanning or plotting a graphic image. The system deflects (10) a portion of the beam of light (18) by an amount dependent upon the value of a characteristic of a signal (12). A plurality of signals is generated (12), each having a different value of the characteristic. Portions of the beam are deflected along paths (15), such that the pixels created by one portion are disposed along one scan line, while pixels of the other portion are disposed along a successive scan line.

Abstract: An improved method and apparatus for generating halftone images using a beam of variable intensity. A look-up table that is accessed, at a minimum, by position coordinates and image intensity data provides beam intensity information. In certain embodiments, the look-up table may be accessed by dot set identification data and/or randomly generated numbers in addition to the position coordinates and the image intensity data. The position coordinates (x,y) may be generated by performing a coordinate transformation on the beam position coordinates (u,v). The beam intensity data stored in the look-up table may permit the formation of soft dots, i.e. halftone dots that are formed by different levels of beam exposure. The look-up table also permits an increase in dot frequency in the middle tones.

Abstract: Apparatus and method for determining whether a specific spatial relationship exists among physical spatial entities. First, spatially significant descriptors such as the interior and boundary of the physical spatial entities are selected and sets of elements forming a representation of each of the descriptors for each spatial entity is determined. Intersections are then determined between the sets of elements for every combination of descriptors and these intersections are categorized. The categorized relationships are then combined to determine a unique mathematical relationship between the spatial entities. The specific spatial relationship to be analyzed is broken down into the set of desired mathetmatical relationships.

Abstract: A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU.

Abstract: A system for processing video data to be displayed comprises a controller and a monitor. The controller includes a memory for storing the digital data to be displayed and apparatus for sequentially reading data from the memory. The data from the controller is conducted in digital form to the separately housed monitor separated from the controller. In the monitor, the digital data is converted into analog form and displayed. In the converting process, the digital data is first converted to an analog current and then the analog current is converted to a voltage. An additional voltage-to-voltage conversion may occur to isolate the capacitance of the display device. This system is particularly suited for high resolution systems (greater than 1000.times.1000 pixels) in which a new pixel is refreshed at least every 10 nanoseconds.

Abstract: A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and selectively enableable instruction prefetch logic. The cache and memory management system includes a system interface for coupling to a systems bus to which a main memory is coupled, and is also comprised of a processor/cache bus interface for coupling to an external CPU. As disclosed, the cache memory management system can function as either an instruction cache with instruction prefetch capability, and on-chip program counter capabilities, and as a data cache memory management system which has an address register for receiving addresses from the CPU, to initiate a transfer of defined numbers of words of data commencing at the transmitted address.

Abstract: A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface, and an execution unit. The instruction interface controls communications with the external instruction cache and couples the instructions from the instruction cache to the microprocessor at very high speed. The data interface controls communications with the external data cache and communicates data bidirectionally at very high speed between the data cache and the microprocessor. The execution unit selectively processes the data received via the data interface from the data cache responsive to the execution unit decoding and executing a respective one of the instructions received via the instruction interface from the instruction cache.

Abstract: In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascending locations of stored data from the cache memory. In an illustrated embodiment, the cache memory stores four words per addressable line of cache storage, and accordingly quad-word boundary registers determine boundary limits on quad-words, quad-word line registers store, in parallel, a selected line from the cache memory, and a quad-word boundary detector system determines when to prefetch the next set of quad-words from the cache memory for storage in the quad-word line registers.

Abstract: An instruction execution accelerator for a pipelined digital machine with virtual memory. The digital machine includes a pipelined processor which on memory accesses outputs a virtual address to a data cache unit (DCU). On particular memory accesses, such as store or similar operations, the pipelined processor can be advanced or accelerated to the next instruction once the memory access is known not to cause a page fault. The pipeline accelerator includes a small associative memory which the page number of a target address of a store operation is compared. If there is a match, it is know that the target address relates to a page within the real memory and the instruction can complete asynchronously. Otherwise if there is no match, the page address is inserted in the associative memory to become the most recent addition. On the recognition of a page fault by the DCU, the associative memory will be cleared to make room for the new entry and others.

Abstract: A height adjust mechanism which may be advantageously used to set a keyboard to a predetermined number of angles with respect to a support surface upon which the keyboard sits. The apparatus is integral with the keyboard base and includes an adjustment foot member having a ratchet surface with four detents therein. The foot member is pivotally mounted within the keyboard base and extends downward through a hole in the keyboard base. An adjustment lever is also pivotally mounted within the keyboard base and includes a pawl which engages one of the detents of the adjustment foot member. A single spring is connected to the adjustment foot and to the adjustment lever. This spring biases the adjustment foot in a downward direction, while at the same time biasing the adjustment lever so that the pawl positively engages one of the detents of the ratchet surface.

Abstract: A hidden panel connector for an electronics enclosure having a removable cover member and a fixed cover member. The fixed cover member is provided with a curved member which projects from the fixed cover member and curves in an upward direction. The removable cover member is provided with a cam member which slideably engages the curved portion so that the removable cover member is vertically rotatable about the fixed cover member. Each cover member has a periphery with lips disposed thereon, which lips engage one another to provide additional stability. Each of the cover members also includes an interlocking member. The interlocking members are engageable with one another to prevent the removable cover member from being vertically displaced from the fixed cover member. The curved cam and interlocking members are integral with and disposed on the inside walls of the fixed and removable cover members to provide a connector hidden on the inside of the electronic enclosure.

Abstract: A deflection circuit for a television includes two semiconductor switching elements connected in series. Separate control circuits are provided for each semiconductor switching element to control the operation of the respective switching element. Each control circuit receives a control signal and is connected to a voltage source. For the control circuit associated with the switching element which receives the highest voltage, connection to the voltage source and the control signal is through diodes which provide common mode isolation. This control circuit includes a capacitor which provides energy for the control circuit when the diode connecting it to the voltage source is reverse biased.

Abstract: A vector to raster converter system in which vectors are delivered to the system and stored in a vector memory in groups. Each group includes all vectors which have at least a portion in a particular area of the output plot called a vector band. Vectors are serially read out of the vector memory and converted into a series of coordinates of points along the vector. The coordinates of each point are analyzed to determine if the point lies in a second particular area within the vector band called a raster band. The coordinates in the raster band are stored in a raster memory. After the entire vector band has been rasterized the contents of the raster memory are output to a plotter. The contents of the vector memory is then rasterized again and a determination is made as to whether each pair of coordinates is in the next raster band. This process continues until all of the raster bands in the vector band have been processed.

Abstract: Apparatus for determining the position of a cursor with respect to a floating coordinate system, such as a menu. The floating menu incorporates two sensing devices similar to that in the cursor. A processing unit determines the position of the two sensing devices and the position of the cursor with respect to a fixed coordinate system. From this data the position of the cursor with respect to the floating menu is determined.

Abstract: .[.The invention provides a.]. .Iadd.A .Iaddend.scanner system .[.which.]. in one embodiment includes only a single moving part in the document path, namley a drive roll, which serves not only to move the document through the system, but also to provide a backing against which the document is pushed while a proximate region thereof is being scanned. .[.The invention in an.]. .Iadd.An .Iaddend.embodiment also provides an opto-mechanical assembly that is shock-mounted to the frame of the system at only three-spaced apart locations, so that the assembly tends to be isolated from vibration and torsional forces.