Abstract: A method for resolving ambiguities in user input to a computer-aided drawing package. The number of necessary commands is therefore reduced. To draw an element, the user selects a particular drawing command. The user then manipulates a pointing device to select points that further define the position and shape. In accordance with the invention, the point selections can be interpreted in more than one way. A region surrounding at least one of the selected points is divided into so-called intent zones. After this point is selected, the drawing package monitors cursor movement through this region. The particular intent zone that the cursor traverses determines the interpretation of the point selections following the command.

Abstract: An improved graphics processor is of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine. The buffer is also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine. The improvement in a preferred embodiment utilizes a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer. User access via an application is provided only to the normal FIFO, whereas system level code is provided access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor. In a further embodiment, a logical sync FIFO is employed also. The sync FIFO is used in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing. Related methods are also provided.

Abstract: A method for positioning a cursor relative to a reference position on the display using the pointing device includes the steps of positioning the cursor at a position on a display with a pointing device, selecting the position as the reference position, the reference position associated with an object, moving the cursor to a plurality of cursor positions not associated with the object on the display with the pointing device, and displaying a plurality of offset values on the display, the offset values being calculated in response to the reference position and the plurality of cursor positions.

Abstract: A method for maintaining relationships between entities in a computer system, each entity having a plurality of nodes, includes the steps of: modifying one of the plurality of nodes; searching for a plurality of dependent nodes from the plurality of nodes coupled to the one node; ordering the plurality of dependent nodes into an order; and evaluating the plurality of dependent nodes in the order.

Abstract: A method for manipulating a first three-dimensional object, in a computer system including a display, a first software application, and a second software application. The method includes creating a model of the first three-dimensional object with the first software application, which has a first three-dimensional coordinate system. Storing the model of the first three-dimensional object in a model format is also included. The method includes retrieving the model of the first three-dimensional object in the model format into a second software application, the second software application having a second coordinate system, and manipulating a view of the model of the first three-dimensional object with the second software application and within the second coordinate system.

Abstract: A content-addressable memory wherein match transistors are prevented from discharging a match line by either placing transistors in series with the match transistors and only turning them on during a match sensing period, or a match sense line which is driven near the precharge voltage of the match line until the match sensing period. The match sensing line also provides charging current to recharge the match line. For some applications, a differential match line amplifier is used to detect matches and mismatches. The match sense line can be used with a CAM having a four-transistor comparator. The invention is also applicable to match lines in programmable-array logic (PAL) cells, and for either NMOS or PMOS circuits.

Abstract: An improved system for administration of license terms for a software product on the network, having an arrangement, for tracking software product usage, with one of the computers acting as a license server. This arrangement permits the license server (i) to identify the current set of nodes that are using the software product, (ii) to handle license data concerning conditions under which usage of the software product is permitted at any given node, and (iii) to determine whether at any given time the conditions would be satisfied if a given node is added to this set of nodes. The software product may thus include instructions to interface with the license server to cause enforcement of the license terms. The improvement, in one embodiment, to the system includes a policy server database maintained on each node, containing data specifying conditions under which usage of the software product is permitted on the corresponding node.

Abstract: A system that permits the plotting of any combination of several colors in one pass. Three differently colored light sources are provided, and thus one, two or three colors may be plotted at the same time. An apparatus is provided for causing relative movement between the scanning head and the substrate along each of the two axes of the substrate. Preferably, the first axis is disposed circumferentially about a cylinder, on which the substrate is situated, the cylinder having a central axis, and the second axis is disposed approximately parallel to the central axis. The system includes deflection means, preferably acousto-optical modulators, for deflecting along a path a portion of each beam of light by an amount dependent upon the frequency of a signal that is present at the deflection means' input.

Abstract: A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.

Abstract: An ink-jet apparatus in which a recorded image is read to provide a image reference signal for comparison with an image recording signal, the resulting comparsion being used as a basis for diagnosing an ink injection state of a recording head nozzles in order to determine and implement an ink injection recovery process.

Abstract: A clock generator generates repetitive master clock pulses, each master clock pulse having a leading edge and a trailing edge. The time interval between the leading edge of a first master clock pulse and the leading edge of a second master clock pulse defines a single clock cycle. A write pulse generating circuit generates write pulses for writing data into a multi-port RAM, and a read pulse generating circuit generates read pulses for reading data from the RAM. When simultaneous reading and writing of data is requested in a particular clock cycle, the leading edge of the write pulse is generated in response to the leading edge of the first master clock pulse before the leading edge of the second master clock pulse. The leading edge of the read pulse is generated after the leading edge of the write pulse, such that the data written into the memory can be read out of the memory during the same clock cycle through a different port with the only common connection being the memory cells.

Abstract: A system is disclosed which enables a user of a computer system to have direct control over the priorities assigned to the execution of tasks requested by the user. The user establishes a user tolerance level indicative of the delay the user is willing to tolerate before a task is assigned to background manager. Then whenever a task is requested by the user, a calculation is made to determine whether the task will require more or less time than the user tolerance. If the task requires more time, it is assigned to the control of a background manager, while if it requires less time, it is executed to completion immediately without further instruction from the user. The background manager handles the execution of all background tasks, maintaining the proper order for data consistency, yet allowing the user to rearrange execution priorities when necessary.

Abstract: A control module for controlling a data register, a self-clocking data register controlled by such a module and a pipeline of self-clocked pipeline registers. The localized control module includes a flip-flop for indicating whether the data register being controlled is occupied or vacant. Each module includes state machine logic for generating an enable output to the pipeline register when the flip-flop indicates the register was vacant and a load signal indicating data is available for loading into the register has been received. The localized control may be further modified to provide look-ahead in which an enable output is also generated when a load signal has been received and an unload signal has been received.

Abstract: A rotatable image-mounting drum for use in a scanner or plotter. The drum has an end for permitting the releasable attachment of the drum to the scanner's or plotter's supporting and turning means. The drum's image-mounting surface and the drum's attachment end are preferably made of the same material, preferably acrylic. The attachment end of the drum includes a disk at the end of the drum, which has an opening or openings passing from its outer face to its inner face. The other end of the drum preferably is not attached directly to the rest of the scanner. The plotter's or scanner's mechanism for releasably attaching the rotatable drum includes a drum mount rotatable by a motor. A clasp stem, passing through a drum-mount opening, has a clasp finger rigidly attached thereto. A cam surface, having a varying elevation, can be rotated so as to push the cam stem through the drum-mount opening. A spring urges the stem against the cam surface.

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.

Abstract: In a computing system of the type which executes instructions having the form A op B=B, a floating point register includes a plurality of addressable storage elements for storing operand data. A first address receiving circuit receives the B operand address from a first instruction, and a second address receiving circuit receives the A operand address from the first instruction. The A and B operand addresses are each used for addressing one of the plurality of floating point register storage elements. An instruction executing circuit performs a function designated by the first instruction on the operand data output from the floating point register and generates result data. The instruction executing circuit includes an exception circuit for generating exception data indicating whether an exception occurred when the function was performed. A shift register has a plurality of storage elements for storing address and control information.

Abstract: An adder adds a displacement address to a base address to generate a virtual address. The adder includes carry indicating circuitry for generating a carry indicating signal indicating whether the addition of the displacement address to the base address resulted in a carry. Addressing circuitry addresses the translation memory with a subset of bits from the base address so that the translation memory outputs multiple address translation entries simultaneously. At approximately the same time the translation memory outputs the multiple address translation entries, the adder completes the addition of the displacement address to the base address and generates the carry indicating signal. A multiplexer selects one of the address translations output from the translation memory in response to the carry indicating signal.

Abstract: A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias are placed near conductive vias to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals (e.g. CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

Abstract: A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition of a second plurality of bits together with a carry from the addition of the first plurality of bits results in a carry, and a second carry chain circuit selectively generates a second carry-out signal indicating whether the addition of the second plurality of bits without a carry from the addition of the first plurality of bits results in a carry. Selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, selects either the first carry-out signal or the second carry-out signal in response to the carry-in signal.