Patents Assigned to Intergraph Corporation
  • Patent number: 5986669
    Abstract: A method for determining data characterizing a primitive resulting after the primitive has been subjected to clipping determines the data after the primitive has been clipped. The data, which may be attribute data, is not determined prior to clipping, thereby saving processing time if the primitive is clipped entirely from view (i.e., a viewing plane displayed on a display device). The primitive initially is defined by a set of initial vertices and a set of attributes associated with the initial vertices. After each instance of clipping, the primitive becomes a resulting primitive defined by a modified set of vertices that may include a new vertex and a modified set of attributes associated with the modified set of vertices.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: November 16, 1999
    Assignee: Intergraph Corporation
    Inventor: Dale Kirkland
  • Patent number: 5977965
    Abstract: A method, apparatus, and computer program product for building at least a portion of a motion picture on a computer system first monitors memory in the computer system for the creation of a frame of the motion picture. It consequently sets a flag in the computer system when it detects that the frame has been stored in the memory. Once the flag is set, the rendered frame is directed to a motion picture builder. Each frame in the portion of the motion picture being built is processed in this manner until the motion picture portion is formed.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: November 2, 1999
    Assignee: Intergraph Corporation
    Inventors: Richard W. Davis, III, James Turner
  • Patent number: 5917502
    Abstract: A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: June 29, 1999
    Assignee: Intergraph Corporation
    Inventors: Dale L. Kirkland, Cynthia E. Allison, James P. Turner, Joseph C. Terry, Jeffrey S. Ford
  • Patent number: 5912746
    Abstract: A scanner for scanning an image on a large-format medium and generating image information. The scanner includes a secondary substrate mounted to the frame and having a length spanning the width of the medium, and a plurality of sensor boards disposed on the secondary substrate. A plurality of sensor dies are mounted on each of the sensor boards. The scanner further includes a lens strip, mounted to the frame between the sensor dies and the moving means. Preferably, a die on each end of each sensor board overhangs the end of the board, and the sensor boards are mounted on the secondary substrate so that dies overhanging ends of the sensor boards are butted against each other.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: June 15, 1999
    Assignee: Intergraph Corporation
    Inventors: J. Thomas Cilke, Gregory A. Baxes, Curtis A. Lipkie
  • Patent number: 5910804
    Abstract: A method for manipulating a first three-dimensional object, in a computer system including a display, a first software application, and a second software application. The present method includes the step of creating a model of the first three-dimensional object with the first software application, which has a first three-dimensional coordinate system. A step of storing the model of the first three-dimensional object in a model format is also included. The present method further includes the step retrieving the model of the first three-dimensional object in the model format into a second software application, the second software application having a second coordinate system. The present method also includes the step of manipulating a view of the model of the first three-dimensional object with the second software application and within the second coordinate system.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: June 8, 1999
    Assignee: Intergraph Corporation
    Inventors: Mark D. Fortenbery, Cameron M. Stubbs, Dominique J. Payannet, Robert Patience
  • Patent number: 5892654
    Abstract: A computer system having an air cooling path includes a motherboard, a circuit board having an edge connector for mounting onto the motherboard, and a chassis defining an interior for containing the circuit board and motherboard. The chassis includes a rear panel having an inset access for accessing the circuit board, where the inset access is spaced inwardly from the rear panel. The computer system further includes an interior panel (within the interior of the chassis) that is connected to the rear panel at a connection location on the rear panel. The connection location is spaced apart on the rear panel from the inset access. The motherboard is mounted to the interior panel, while the rear panel defines a vent between the inset access and the connection location. The interior panel, motherboard, and vent define the air cooling path across the circuit board.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: April 6, 1999
    Assignee: Intergraph Corporation
    Inventor: Curtis W. Worden, Jr.
  • Patent number: 5878216
    Abstract: A system and method for controlling a slave processor from a master processor in which the slave processor is instructed to await the occurrence of a particular event and the arrival of a number of data words before processing additional requests. A wait request from the master processor includes identification of an event which must occur before processing is to resume. The master processor provides a number to a register accessible to the slave processor to indicate how many data words to await. The slave processor discontinues processing upon receiving the wait request. The slave processor detects the occurrence of the event and the arrival of the data words and then resumes processing. The register may include an indicator or flag that indicates when the number of data words set by the master processor has been received.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: March 2, 1999
    Assignee: Intergraph Corporation
    Inventors: David W. Young, Jeffrey J. Holt
  • Patent number: 5864512
    Abstract: This invention relates to providing high-speed video graphics through use of single ported memory chips on the video card.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: January 26, 1999
    Assignee: Intergraph Corporation
    Inventors: Matt E. Buckelew, Stewart G. Carlton, James L. Deming, Michael S. Farmer, Steven J. Heinrich, Mark A. Mosley, Clifford A. Whitmore
  • Patent number: 5852372
    Abstract: Transceivers for bus communications using GTL-type transmission-line bus structures provide improved clamping of an initially ON output pulse of a communication bus driver and adds an active pull-up function inside the integrated circuit that does not change the external circuit nor require additional functional external circuit corrections. Receivers may contain an active pull-up for added signal quality improvement Improved clamping and active pull-up allow reduced width of the channel of the N-channel CMOS output transistor. A drive/receive clamp may be added to a sequential pull-up circuit and an active pull-up circuit for better performance at higher frequencies. A related method may comprise first switching OFF an active pull down circuit and switching ON an active pull-up circuit, where the active pull-up circuit clamps the driver output voltage from falling below a first voltage.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: December 22, 1998
    Assignee: Intergraph Corporation
    Inventors: Eduard F. Boeckmann, Vern Brethour, Vahid Samiee
  • Patent number: 5835095
    Abstract: Objects are represented in a coordinate space which is twice scanned by scan lines, once in one direction and then once in another direction. At each scan line, a list of line segments is generated, where each line segment represents the intersection of the projection of a polygon and the scan line. The segments are then examined to determine which are visible segments, using the z values of the end points of the segments. The visible segments of a scan line are compared to the visible segments of a previous scan line or an accumulation of visible lines, and if the end points of a visible segment taken from a polygon differ by less than a threshold amount, the lines formed between end points in one scan line and the adjacent scan line are considered to be visible lines. Where the two scans are a horizontal scan and a vertical scan, the threshold amount for vertical scans is the distance between horizontal scans and the threshold amount for horizontal scans is the distance between vertical scans.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: November 10, 1998
    Assignee: Intergraph Corporation
    Inventors: Karin P. Smith, George R. Smith, Jr.
  • Patent number: 5831637
    Abstract: A 3D graphics processing system in a preferred embodiment has an input for a digital video data stream. The system has a graphics engine, for processing graphics request code and data, in communication with a host computer over a data bus and also in communication with a frame buffer. It also has an input for a digital video data stream, and the input is in communication with the graphics engine. A control arrangement interrupts processing by the graphics engine of conventional graphics request code and data to permit priority processing of the digital video data stream. In this manner, an image associated with the digital video data stream may be displayed in real time in a desired plane that may be accessed and processed by the graphics processing system as a graphic image.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: November 3, 1998
    Assignee: Intergraph Corporation
    Inventors: David W. Young, Jeffrey J. Holt, James Leroy Deming
  • Patent number: 5822188
    Abstract: A system for cooling a circuit board within a chassis having an interior and an interior wall includes a member that extends between the interior wall and a face of the circuit board. To that end, the system further includes an inlet formed in the chassis for receiving air to cool the circuit board, an outlet formed in the chassis for ejecting air from the interior of the chassis, and the member. The member may physically contact the face of the circuit board.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: October 13, 1998
    Assignee: Intergraph Corporation
    Inventor: James R. Bullington
  • Patent number: 5801714
    Abstract: A device is provided for managing vertex lists. In particular, in one embodiment, the device permits management of the communication, in a digital computing system having a graphics processor, of a sequence of data records associated with successive vertices. The vertex data are typically used for drawing polyline figures or triangular mesh, or other figures using coordinates. Each record includes at least one floating point value that provides at least a first datum associated with a vertex. The device comprises an arrangement for placing the sequence of data records in a data stream, as well as an arrangmement for placing at the end of the data stream a data record in which the floating point value providing the first datum is set to a value corresponding to Not a Number. In this manner it can be established when the sequence of records is complete without the need for any extra control bits. Related methods are also provided.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: September 1, 1998
    Assignee: Intergraph Corporation
    Inventor: Jeffrey J. Holt
  • Patent number: 5798923
    Abstract: A system for deriving a cartographic projection having minimum distortion with respect to selected elements of distortion. A first function contains modifiable parameters for mapping earth coordinates into two-dimensional coordinates on the surface of a map, the parameters being varied in such a way as to minimize a function containing a selected set of distortion components normalized according to a predetermined set of relative weights. The selected distortion components may include distortion with respect to distance, angle, and area.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: August 25, 1998
    Assignee: Intergraph Corporation
    Inventor: Peter Laskowski
  • Patent number: 5799204
    Abstract: A high-performance video controller is provided for a microprocessor-based computer having a bus, which has a plurality of slots for receiving slot connectors for peripheral-type devices, wherein (i) the bus is of the type imposing a single-device-per-slot limitation and (ii) the computer has a BIOS requiring on boot-up of the computer the presence of a standard video controller (e.g. VGA). The high-preformance controller includes (a) a connector arrangement having at least one slot connector, and (b) a standard-video-controller subsystem coupled to the connector arrangement and having a video output, and (c) an advanced graphics subsystem that is also coupled to the connector arrangement and that also has a video output. The connector arrangement may have a plurality of slot connectors so that the standard-video-controller subsystem is connected to a separate slot from the advanced graphics subsystem, which also has its own slot.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: August 25, 1998
    Assignee: Intergraph Corporation
    Inventor: William Steve Pesto, Jr.
  • Patent number: 5794037
    Abstract: A computer system provides multiple unprotected applications direct access to a slave processor. The host processor issues context switching requests to save and restore partially completed unprotected requests in the slave processor.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: August 11, 1998
    Assignee: Intergraph Corporation
    Inventor: David W. Young
  • Patent number: 5794003
    Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: August 11, 1998
    Assignee: Intergraph Corporation
    Inventor: Howard G. Sachs
  • Patent number: 5790461
    Abstract: Control circuitry for a register file is provided which allows immediate or rapid output of input write data by bypassing the need to store the data and then read it out of the register file. In each pairing of memory cells, the read line is coupled to both the storage cell and to the write line. The connection to the write line is configured so that, when the connection is activated, such as by turning on a transistor, the magnitude of the data signal provided from the write line to the read line is large enough to overpower whatever signal is being output to the read line from the memory cell. In this way, when the connection from the write line to the read line is activated, the write line will output the information on the read line, rather than the information in the storage cell. The information on the read line can then be output onto the write line without the information first being stored in the memory cell.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: August 4, 1998
    Assignee: Intergraph Corporation
    Inventor: John C. Holst
  • Patent number: D401915
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 1, 1998
    Assignee: Intergraph Corporation
    Inventor: Terry W. Johnson
  • Patent number: D408373
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: April 20, 1999
    Assignee: Intergraph Corporation
    Inventor: Terry W. Johnson