Abstract: A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition of a second plurality of bits together with a carry from the addition of the first plurality of bits results in a carry, and a second carry chain circuit selectively generates a second carry-out signal indicating whether the addition of the second plurality of bits without a carry from the addition of the first plurality of bits results in a carry. Selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, selects either the first carry-out signal or the second carry-out signal in response to the carry-in signal.

Abstract: A master clock generates master clock pulses having a selected frequency. A data clock generates a first data clock pulse corresponding to the leading edge of each master clock pulse and a second data clock pulse corresponding to the trailing edge of each master clock pulse. The first and second data clock pulses are applied to an input node of the data circuit. The data circuit generates a first data signal at an output node in response to the first data clock pulse and a second data signal at the output node in response to the second data clock pulse. There is a selected delay between the time a data clock pulse is applied to the input node and the time a data signal appears at the output node. First and second memory elements are provided for storing the data signals from the data circuit.

Abstract: A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB.

Abstract: A system for supplying input data establishes the location of data points in a model space represented in a view of a two-dimensional display. In one embodiment, the system has a pointing device (such as a mouse) for establishing the location of a cursor on the display, and also an arrangement for establishing in the model space primary and secondary orientation planes of which one is currently active at any given time. The embodiment also has an arrangement for providing an initial value (called the "start point") of a tentative point in the model space. A dynamic arrangement establishes a current point in a construction plane, parallel to the active plane, in which the tentative point is located, in the location attributable to the position of the cursor on the display of the view.

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption.

Abstract: A content-addressable memory wherein match transistors are prevented from discharging a match line by either placing transistors in series with the match transistors and only turning them on during a match sensing period, or a match sense line which is driven near the precharge voltage of the match line until the match sensing period. The match sensing line also provides charging current to recharge the match line. For some applications, a differential match line amplifier is used to detect matches and mismatches. The match sense line can be used with a CAM having a four-transistor comparator. The invention is also applicable to match lines in programmable-array logic (PAL) cells, and for either NMOS or PMOS circuits.

Abstract: An arithmetic unit wherein a plurality of electrical signals corresponding to the mantissa is shifted and a bit signal corresponding to the sticky bit is calculated simultaneously with the calculation of the shift count. Initially, a serial approach to mantissa shifting and sticky bit calculation is employed. A parallel approach to matissa shifting and sticky bit calculation is adopted when all shift count bits are available. In one embodiment of the present invention, an exclusive OR gate is used to calculate the difference between the least significant bits of the first and second exponents. A shifter/sticky bit calculator immediately acts upon the output of the exclusive OR gate and begins shifting the mantissa and calculating the guard, round, and sticky bits. The more significant bits of the shift count are progressively generated thereafter, and the guard, round and sticky bits are calculated and the mantissa is shifted as the shift count bits become available.

Abstract: Dynamic segmentation of Geographical Information System (GIS) map data, stored in a relational database, converts linear-feature fixed-length attribute arrays, stored as columns in a relational table, into variable length attribute and location arrays for inclusion into an object-oriented map database which can be scanned for candidate values in the attribute and location arrays meeting certain search criteria. Selection of the scanned values is provided for. The object-oriented database may be queried to return the regions, specified in region coordinates, in each of the variable length location arrays, corresponding to the selected attribute values. The intersection of found regions with the selected values from the value arrays can be thereby determined.

Abstract: A rotatable drum for use in a plotter, or similar device, that provides vacuum for holding the film or other media to the drum's surface, so as to easily accommodate films of various sizes. The drum includes first and second journals and a plate mounted on the circumference of the first and second journals. At least one of the journals has defined on its circumference circumferential channels. The plate has interior and exterior sides, and the first and second journals and a portion of the plate's interior side define a chamber. The plate's exterior side has defined thereon a plurality of grooves. In one embodiment, at least one of the grooves, associated with a first film size, is in fluid communication with the chamber, and some of the remaining grooves, associated with the larger film sizes, are in fluid communication with the channels. A vacuum is supplied to the chamber, and a valve is provided for controlling fluid communication between the channels and the chamber.

Abstract: A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias are placed near conductive vias to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals (e.g. CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

Abstract: A mechanism for clamping a flexible metal printing plate to the circumferential surface of a rotatable plotter drum is provided. The clamping mechanism includes a mounting member affixed to the drum's surface. The mounting member has a passage aligned radially with respect to the drum. A slidable member extends through the passage and past the drum's axis of rotation. The slidable member has, at one end, a head and, at the other end, a weight. The clamp head is disposed further from the axis of rotation than the mounting member and adjacent the drum surface so as to permit clamping between the head and the drum surface. The slidable member is disposed so that its center of mass is opposite the drum's axis of rotation from the head. A mechanism, such as a compressed spring mounted between the weight and the mounting member, is provided for urging the slidable member so as to force the head towards the drum surface. An actuator having two modes is also provided.

Abstract: A fully associative translation lookaside buffer (TLB) using a content addressable memory (CAM) array to store virtual addresses and a static random access memory (SRAM) array to store corresponding physical addresses. The TLB incorporates a logic circuit that allows the SRAM to be accessed during both associative and non-associative modes by word lines that are strictly a function of corresponding match lines. Additionally, the logic circuit incorporated in the TLB does not introduce any additional delay in outputting the physical address from the SRAM during the associative mode.

Abstract: An apparatus for capture of image data from an object has a detector array containing at least one detector row, and arrangements for rotating the detector array relative to the object, as well as for moving the object and the detector array relative to one another in a desired direction of scan. A control arrangement causes the detector array to be rotated to a desired orientation with respect to the object based on information in the object and causes the object to be scanned by the detector array in such a way that the detector row is at right angles to the direction of scan. A similar method is also provided.

Abstract: A semiconductor memory having a redundant column is described in which access time is not reduced when the redundant column is employed to replace a defective column. The memory includes a number of columns of memory cells, each column having a corresponding input/output node. A set of input/output lines, the set typically being one smaller than the number of columns, is connected to a corresponding set of switches. The switches connect each input/output line to one, and only one input/output node chosen in response to a control signal supplied to the switch. By having positioned all of the switches on the left side of the defective column to connect to columns to the left of their respective input/output connections, and by positioning all of the switches on the right side of the defective column to connect to the columns on the right side of their respective input/output connections, the defective column is removed from operation without increase in propagation delays.

Abstract: A method for reproducing images using rotated screens, wherein the rotated screens are formed by the replication of a screen tile (ABCD). The screen tile (ABCD) is based on a seed screen cell (11, 17) that is disposed at the desired angle of screen rotation, theta, and is replicated so as to fill the screen tile. Thus, the screen can be generated by replicating the screen tile with respect to the same coordinate system as that identifying addresses for the image data being screened, i.e., without rotating the screen tile. Both the screen tile and the seed screen cell (11, 17) are represented by matrices. Noise (51) can be introduced into process of forming the screen in order to further lessen Moire patterns.

Abstract: A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the processor. The modifiable translation logic includes modifiable read-write memory, while the non-modifiable translation logic includes fixed combinational logic for providing predefined translations of predetermined virtual addresses to real addresses. A controller selectively accesses main memory on cache memory misses to load translation information and other data from main memory to the cache memory. In a preferred embodiment, the address translation logic provides an associated system tag defining access priorities and access modes with each address translation.

Abstract: The first current flowing terminal of a first MOS transistor is coupled to the first current flowing terminal of a second MOS transistor at a first voltage node; the first current flowing terminal of the third MOS transistor is coupled to a second current flowing terminal of the first MOS transistor at a first output node; the first current flowing terminal of a fourth MOS transistor is coupled to the second current flowing terminal of the second MOS transistor at a second output node; and the second current flowing terminal of the fourth MOS transistor is coupled to the second current flowing terminal of the third MOS transistor at a second voltage node. A transistor control unit is coupled to the gate terminals of the first, second, third and fourth MOS transistors for biasing the transistors for alternately flowing current through the first and fourth MOS transistors or through the second and third MOS transistors.

Abstract: A method and apparatus for measuring capacitances in the pressure of stray capacitances is disclosed. A high frequency voltage signal is applied to a first node of the capacitor being tested. The frequency and change in voltage of the signal is known and measured precisely. The current flowing through the small capacitor is measured during a known portion of the signal's period. The measuring period is chosen so that the stray capacitances charge and discharge during the period, thereby adding no net current to the measured current. As the measured current, frequency, and change in voltage are all known precisely, the capacitance of the test capacitor can be calculated precisely. For testing capacitances in semiconductor wafers, a plurality of test structures comprised of a plurality of test capacitances are fabricated on the wafers. Using known decoding methods and apparatus, individual capacitances within individual test structures can be accessed and measured, using the method of the present invention.

Abstract: A scanning system, having a fixed platen and optical imaging system and a translated reference scale, is provided for scanning of a modulated light beam (or a set of parallel, independently modulated light beams) onto an object surface. The optical system provides a combined light beam including the modulated light beam and a reference light beam. An optical imaging device moves the combined light beam along a scan line, and a translatably mounted beam splitter splits the combined light beam to direct at least some of the reference light beam onto a reference scale and a sensor. The reference scale sensor, which is rigidly attached to the beam splitter, and is responsive to reference beam position in two directions, provides a clocking signal indicative of beam position along the scan line and a vernier position signal indicative of beam position in a direction transverse to the scan line.

Abstract: An apparatus for stiffening a circuit board during soldering, assembly, and repair/rework, which includes an elongated crossmember having two opposing ends, an outer support leg extending downward from each crossmember end to form a bridge support with the crossmember and a central support leg extending downward from a central portion of the crossmember. A central portion of the circuit board is attached to the central support member to prevent the circuit board from softening and sagging when exposed to the heat from soldering.