Abstract: A decoder for Manchester encoded data in which the encoded data is sampled by a clock signal to produce a decoded data signal. The decoded data is combined with a delayed version of the encoded data, to produce the clock signal. In a preferred version, a tuned circuit is included to stabilize the clock signal against jitter.

Abstract: There is described a data processing apparatus with a binary multiplication capability. The apparatus has an arithmetic and logic unit (ALU) and a operand register. The operand register is divided into two portions, the first of which can be shifted while the second is loaded in parallel. For multiplication, the first portion is used to hold a multiplier and to receive the least significant bits of the result, while the second portion receives the most significant bits of the result. The invention avoids the need for a separate shift register to hold the multiplier. The described apparatus also has a look-ahead facility, for selecting the next bit of the multiplier ahead of its requirement, so that it is immediately available when required.

Abstract: A data display control arrangement in which apparatus for scrolling lines of data relative to a display area of a data display apparatus (1) comprises means (2) for producing a selectively controllable scrolling action, the means (2) including a transducer device (16) comprising two groups (18A, 18B) respectively including two sets (20,21) (24,25) of elctrical contact tracks 19 and an elastomeric pad which includes a non conductive member 27 is loaded with conductive material, whereby pressure on the member (27) changes the conductivity thereof and in so doing progressively interconnects the tracks of the sets (20,21) (24,25) to produce analogue signals related to extent of pressure. A converter 9 converts the analogue signals to digital signals which are used to control said scrolling.

Abstract: A method for verifying the design of a digital electronic component in which the component is replaced by a simulation unit connected to the intended host system. The simulation unit has a memory for holding responses to stimuli from the host system. If the required response is not in the memory, it is calculated and placed in the memory, and the operation of the host system is then re-started from the beginning. In this way, the required set of responses is built up incrementally in the memory until, eventually, the operation of the host system can run to completion.

Abstract: A cabinet for housing electronic equipment constructed entirely from plastics material. The cabinet comprises a base and panels all formed with integral parts which interlock to secure adjacent panels together thereby dispensing with the need for any structural framework. The cabinet is provided with a removable panel to allow access to its interior. Cam surfaces on the cabinet engage with complementary cam surfaces on the removable panel when the panel is slid into position to draw it into engagement with the cabinet. The inner surfaces of the panels have conductive coatings to provide screening against radio frequency interference and compressible electrically conductive gaskets are provided between the panels to form airtight seals and to maintain continuity of the screening.

Abstract: A data transformation circuit transforms an input data value into an output value according to a many-to-one mapping scheme by utilizing a hash coding circuit (30) which combines the input data value with a hashing key and a feedback signal. The hashing key is selectively variable and the output of the hash coding circuit is distributed in a selectively variable manner into one of a number of sections of a register (31) to enable the transformation to be modified in a flexible manner.

Abstract: In a data communication system an interface unit connects a device to a common communications channel shared with other devices using e.g. a carrier-sense multiple-access protocol. Individual bytes for a predetermined destination device are supplied by the device to communications controller 6 without any grouping into packets. They are then stored in a RAM 8 under control of a microcomputer 5. As soon as a byte is received, the interface unit attempts to transmit a packet; when the right to transmit is won the interface unit transmits a packet containing that and any subsequent bytes. The length of the packet therefore depends on the delay before a packet can be transmitted, and hence on the loading on the channel.

Abstract: A pipelined data processor is described, which obeys a sequence of instructions each with a read phase in which an operand is read from a memory, an execute phase in which an operation is performed by an execution unit, and a write phase in which a result is written into the memory. The phases of successive instructions are overlapped, and each instruction is stepped on to its next phase at the end of each clock beat. Each clock beat is divided into a write sub-beat followed by two read sub-beats. The write address for each instruction is stored in a write address register and is compared with each read or write address applied to the memory. When these addresses match, the output of the execution unit is either written into the memory (if the match occurs during a write sub-beat) or fed back to the execution unit as an operand (if the match occurs during a read sub-beat).

Abstract: In a computer system bytes passing from a store to a processor pass through a memory (PROM). The contents of locations of the memory which are addressed by data bytes and most operation codes are equal to the respective data bytes and operation codes by which they are addressed so that the memory is transparent to them. However, the contents of some locations are not equal to the op-codes by which they are addressed so that those operation codes are converted into different operation codes.

Abstract: A visual display system having a restricted data display capability incorporating a main buffer store (1) having a storage capacity for data lines greater than the display line capacity of the display (2). Status information signals from a control unit 14 are associated with each line of data as it is introduced into the display so that when the display is scrolled or racked to free data display lines for new data--the status signal effectively decides whether a line of data is discarded or fed into the main buffer store (1).

Abstract: Data processing apparatus is described, comprising an array of data processing elements in rows and columns. Each element has a data register for input/output. Each column of data registers can be interconnected to form a serial shift path containing either (a) the even-numbered registers, (b) the odd-numbered registers or (c) all the registers. This allows data to be shifted out of the array, one row at a time, either from the even rows, the odd rows, or all the rows. Data can be shifted into the array in a similar way. The facility for selecting the even or odd rows is useful for handling interlaced image data.

Abstract: A printed circuit board which facilitates the removal and replacement of components. The circuit board (1) has unplated holes (8) extending therethrough for receiving connection pins (3) of components (2) mounted on one face of the circuit board (1). The pins (3) protrude from the opposite face of the circuit board (1) and are soldered to conductive pads (9) on this face which are connected by surface conductors (10) to plated through-holes (4) linking conductive tracks (6,7) at different layers of the circuit board (1).

Abstract: In a data storage apparatus, memory chips are arranged in groups, each group having an address bus which is connected to the address inputs of all the chips in that group. Each address bus is terminated at both ends by circuits which perform the dual function of suppressing reflections and checking the addresses.Because reflections are suppressed, the time taken to address the store is reduced. One of the termination circuits in each group is arranged to compare the address on the bus with that on the bus in the adjacent group; the other circuit compares the address with a predetermined value.

Abstract: Communications networks are interconnected by a bridge which allows the stations on each network to communicate with those on the other netowrk. Each station has an identifying address unique in the system. Data is transmitted in the form of packets each containing a source address and a destination address. The bridge includes a table holding addresses of stations in the first network. Whenever the bridge receives a packet from the first network, it compares its destination address with the contents of the table, and if no match is found, transmits the packet on to the second netowrk. The bridge also compares the source address of the packet with the contents of the table and if no match is found, enters that source address into the table. Thus, the contents of the table can be built up by the bridge by a learning process. The bridge handles transmission of packets in the opposite direction by a similar method, using a second table, holding the addresses of stations in the second network.

Abstract: In a ring network (1) messages sent from any one of a group of stations (3) to all the remainder include an acknowledgement field (ACK) holding a count preset to equal the number of expected destination stations. Each destination station that successfully receives the message acknowledges by decreasing the count by 1; acknowledgement is withheld if an error is detected in the message or the station cannot accept it. Acknowledgement is performed by a circuit (17) in a loop-through path (15) in an interface unit (4) connecting the station to the network (1). The originating station checks in a circuit (28) if the final value of the count on its return is zero. If so, the originating station is assured that each expected destination has made a positive acknowledgement of successful receipt.

Abstract: A connection arrangement (6) located on the side of a screened sleeve (2) housing electrical cables (1) for connecting the sleeve (2) to a unit of electrical or electronic equipment. The arrangement comprises a frame (17,18,19,20) of conductive material secured to flaps (13,14,15,16) cut in the wall of the screened sleeve (2) so as to form an electrical connection between the frame and the screen of the sleeve. The frame is received into a corresponding aperture (23) in a connection plate (22) on the unit of equipment allowing electrical cables housed in the sleeve to enter the unit through the frame and the connection plate aperture while maintaining the screening at the connection.

Abstract: The system displays linear features on a gray-scale or other multiple-intensity display device with greater apparent smoothness by selecting the intensities of picture elements in the neighbourhood of the feature in dependence on their closest distances to the feature. Straight lines are generated by a vector generator (4) which conducts scans across the line. The closest distance from the picture element currently reached by the scan to the center of the line is held in an accumulator (18), which at each step of the scan is incremented or decremented from a register (20 or 21) holding the change in the distance. Each scan is terminated when a comparator (26) indicates that the intensity has reached that of the background. This scanning technique allows lines of varying width to be displayed easily. The position of the picture element along the line is held in an accumulator 19, used to address a table (22) holding the width at that point. A similar scanning technique is used in a circle generator.

Abstract: A phase locked loop system for receiving a data input with a predetermined bit frequency includes a source (10 D.sub.1 D.sub.2) of clock signals with a frequency nominally equal to the bit frequency of the data signal means (12,13,14,15,16) for dividing each clock period into three regions corresponding to early, normal and late arrival of the data signal relative to the clock signal and means (D.sub.3 D.sub.4 D.sub.5) for deciding which region the data signal occurs in and for respectively advancing or retarding the phase of the clock signal if the data signal occurs in the early or later region.

Abstract: The system forms displays as an array of picture elements each of which can have more than two possible intensities (e.g. a grey scale). The circle generator derives the intensities for elements in and near an arc of a circle to be drawn. The intensity for an element is determined by the closest distance d from the element to an ideal circle characterizing the arc in such a way as to give a smoothed appearance. The distance d is obtained from a distance accumulator (39) and applied, adjusted for the width of the arc, to a sample table (42) holding the intensities. A step sequencer (40) causes the circle generator to execute scans along lines of picture elements across the arc. At each step d is changed by a distance increment or decrement obtained from one or both of two increment accumulators (36) and (37). These in turn are changed at each step by a constant amount obtained from a register (38) and equal to the step size divided by the radius of the ideal circle.

Abstract: In a data storage unit, internal timing signals are produced by scanning a writable control memory. Thus, the timing of the storage unit can easily be varied, simply by re-writing the contents of the control memory. This allows the use of a faster clock rate without the necessity for complete redesign of the storage unit. The basic clock period is sub-divided into a number of sub-periods, allowing the timing signals to be adjusted with an accuracy better than one clock period.