Abstract: A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.

Abstract: Data storage apparatus consisting of an array of RAM chips, with Hamming code checking for detecting double-bit errors. Address signals are fanned-out to the chips by way of driver circuits. Each driver circuit distributes an address bit to only two columns of chips (or in some case, just one column), so that is one of the driver circuits fails, no more than two chips in each row will be affected. Hence, no more than two bits in any data word will be in error, and this can be detected by the Hamming code.

Abstract: A data processing system comprising multiple processing nodes each containing a processor and a data store. The store holds local data, and also holds copies of shared data required by the node. This reduces conflict between the nodes in accessing the shared data. When one node updates the shared data, it sends an update message to all the other nodes over a transmission link. The processor is then free to continue processing. When the message reaches the other nodes, it updates the other copies of the shared data, so as to ensure consistency. Each node receives messages from the link in the same order, and this defines a unique chronological order for the updates, even though the nodes are asynchronous. A node is temporarily suspended if an update occurs out of this correct chronological order.

Abstract: Apparatus for storing a cable (2) in a container (4), the apparatus comprising a pair of spring tensioned pivotted arms (10), (11) mounted within the container (4) and carrying pulleys (5,6). A loop of the cable (2) is formed around the pulleys (5,6) and is expanded by the spring tension of the arms (10,11) to draw the cable (2) into the container (4). As the cable (2) is withdrawn from the container (4) the arms (10,11) move against the spring tension to allow the loop of the cable (2) to contract. A resiliently extensible portion (9) of the cable (2) is also extended during withdrawal.

Abstract: A sequential logic circuit includes means for checking, while the circuit is in operation, that it is stepping correctly from one state to the next. The current state of the circuit is encoded as X0-X3. That encoded value is compared with a predicted value Y0-Y3 derived in response to the previous state of the circuit itself and those signals that cause the transition from the previous to the current state. If the two do not match the circuit has not stepped to the correct state. Reduction in hardware is achieved by allowing certain states to share the same encoded value.

Abstract: A data transmission system is formed from a series of data transmission loops (2). Each loop includes an interface unit (3) for an attached device and is connected at either end to a synchronizing and switching module (5) in a central unit. The loops (2) are connected by the modules (5) into a continuous data-transmission path connecting the interface units in sequence.The interface units 3 each acts as a synchronous repeater and/or a source of fresh data. To prevent the accumulation of jitter in the clock signals derived in the interface units each module (5) contains a first-in first-out buffer (25) in which the data is resynchronized to a common clock source (7) used by all the modules. The modules (5) also bypass any loop which contains an inoperable unit over a link (35).

Abstract: A run-length decoder arranged to produce output signals in groups, each group being output in parallel. The decoder includes a position register which indicates the position, within a group, of the latest transition between signal values. The contents of this register are added to the incoming run-length code so as to calculate the number of groups to be output before the next transition and the position within the group of that next transition. The calculated number of groups is then output and a transition is introduced into the calculated position in the next group to be output.

Abstract: An electrical connector for a multi-pin circuit module in which the circuit module (6) is supported on a carrier (7) slidably mounted on a base unit (2) with its connection pins (10) extending through holes (9) in the carrier (7). Sliding the carrier (7) causes the pins (10) to engage contact elements (4) on the base unit (2) and the arrangement is such that each pin (10) is supported by the carrier (7) in the region of engagement.

Abstract: The device incorporates a support member (1) for the circuit package (13); a plurality of contact elements (4) for connection with the conductive terminations mounted on the support member each of the contact elements being resiliently biassed away from its associated conductive terminations (16) and means (12) for selectively exerting pressure upon the contact elements so as to urge them into contact with their associated conductive terminations to facilitate soldering and after such soldering to facilitate the removal of the circuit package (13) if and when desired, by allowing the pressure to be removed so that on de-soldering the resilient loading on a contact (4) will cause it automatically to spring away from the associated conductive terminations.

Abstract: A data processing network has a plurality of data processing stations which communicate over a bus. Each station is inductively coupled to the bus. Data is transmitted in a binary coded form in which a zero is represented by a pair of oppositely poled pulses and a one is represented by the absence of any pulse. The transmitter circuit includes an energy saving circuit for recovering energy from the backswing of each pulse. Preferably the bus consists of a twisted pair of wires.

Abstract: A data processing system consists of a number of modules such as integrated circuit chips, each of which receives a clock signal. Each module contains a checking circuit producing a failure signal which indicates whether or not the module is operating correctly. The clock signal is used to invert the sense of this failure signal in successive clock periods. Thus, the failure signal normally alternates between two values in successive clock periods, and its phase relative to the clock signal denotes whether or not a failure has been detected. However, if the clock supply to a module fails, or if the checking circuit itself fails, the failure signal from that module no longer alternates, but is frozen at one or other of the two values. This allows failure of the clock supply or of the checking circuit to be detected.

Abstract: An image is scanned by a TV camera 9 and the resultant signal digitized in an analogue to digital converter 12 the output of which represents the measured intensity of each picture element of the image. The values relating to selected lines may be captured in a line store 13. Alternatively the number of picture elements of a selected intensity may be counted during the count of a scan in a level counter 14, using a look-up table 15 as a mask to select the desired level. After all levels have been similarly counted the resultant histogram is modified by mapping each intensity into a new value with a smaller number of bits in such a way as to tend to equalize the number of picture elements in each new level. The new values are loaded into the look-up table 15 and in subsequent scans the measured intensities are converted into the new values, which may be displayed on a monitor 16 or captured in the line store 13.

Abstract: An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally to the southernmost element of the neighboring group, so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction.

Abstract: A communicating network in which encoder/decoders are joined in a ring by transmission links. Data passes over the links as a carrier having two cycles per bit period. The amplitude of the carrier in any bit period is non-zero and represents the value of the bit. In each encoder/decoder the carrier is recovered by a tuned circuit, the clock is recovered by dividing the carrier and the data is recovered. The same carrier is remodulated with the output data. The whole system forms an oscillatory system which sustains the carrier at a frequency which varies if the properties of the ring change.The specification also describes the use of a modulated carrier in conjunction with a filter blocking frequencies below 25 MHz to give good noise immunity.

Abstract: A method or apparatus for facilitating the construction of prototype electronic circuits using printed circuit boards, by providing a printed circuit board 1, with a plurality of through connection bores 15 arranged in rows and columns, and with a conductive pad 4 at each end of each hole. A group of parallel conductive tracks 3 is provided on one face of the board substrate, the tracks 3 extending through the columns of pads 4, and a second group of conductive tracks 12 is provided on the other face of the board substrate, the tracks 12 being perpendicular to the tracks 3. The tracks 3 and 12 are connected to selected ones of the pads 4. In addition, conductive planes 5,9 are provided between the said first and second faces of the substrate, these planes being connected with selected ones of the plated through connections 15. Certain of the connections 15 are used for the purposes of mounting the connector pins of components.

Abstract: A cable clamping arrangement (2) for an electrical connector arranged to hold a cable or bundle of wires (7) firmly in place so as to provide strain relief to the wire terminations. In the described embodiment the cable (7) is clamped by being urged into a pair of V-notches (5) formed in a hollow member (3). In one form of the device a flexible tie (8), extending through the interior of the hollow member (3), pulls the cable (7) into the V-notches (5). In other forms of the device the cable (7) is pulled into the V-notches (5) by a rigid hook (11) also extending through the interior of the hollow member (3).

Abstract: A binary-coded-decimal to binary converter employs a selection network to which the binary coded decimal digits are applied, the digits being selected in pairs of increasing order of decimal denominational significance to be passed to the address lines of a pair of memory elements, the locations of which contain the binary terms equivalent to the decimal digits from which the particular location address is derived. In order to increase the effective utilization of the memory elements, the binary code components specifying at least one of the decimal digits are manipulated by the selection network, for example by conversion to complementary form, before being applied to the address lines.

Abstract: A negative resistance element having two terminals (11, 12;) a resistor (R1-4) connected in a path between the terminals, and a current mirror arrangement (T1, T2; T3, T4;) responsive to a current flowing into the first terminal (11) to produce a current through the resistor R1-4 in such a direction as to increase the voltage of the second terminal 12 relative to the first terminal 11.

Abstract: An array processor consisting of a plurality of sections (S1, S2-S9), with switching means (24,26,30,32) selectively operable to by-pass any one of the sections so as to effectively remove it from the system. One of the sections normally acts as a stand-by, and is by-passed. However, if one of the other sections fails, that section is by-passed and the stand-by is returned to service. The currently active sections are allocated sequential addresses.

Abstract: A voltage controlled negative resistance with two terminals (12,13; 15,16; 19,20) and first and second current paths connected between the terminals. A current mirror arrangement (T2, T3; T5, T6, T7, T8; T9, T10) so controls the current in the second path in accordance with the value of the current in the first path such that any variations of current in the second path are larger than in the opposite sense to variations of current in the first path.