Abstract: The switching di/dt and switching dv/dt of a MOS gate controlled ("MOS-gated") power device are controlled by respectively controlling the voltage and current waveforms. Open loop control of the turn-on of the MOS-gated device is provided by coupling a common terminal of a current generator circuit, which provides a current to the gate of the MOS device, to a first resistor for controlling the switching dv/dt. At the detection of a negative dv/dt, the common terminal of the current generator circuit is then coupled to a second resistor for controlling the switching di/dt. The first and second resistors are, in turn, coupled to the source terminal fo the MOS-gated device. An analogous operation provides turn-off control of the MOS-gated power device. Closed loop control is also provided by measuring the switching dv/dt and the switching di/dt which are then fed back to the circuit to control the current supplied to the gate of the MOS-gated device.

Abstract: A semiconductor device includes a guard ring in the termination area that is formed using the same processing steps that form the active area of the device and without requiring additional masking steps or a passivation layer. The guard ring is formed in an opening in the field oxide located in the termination area and is electrically connected to a polysilicon field plate that is located atop a portion of the field oxide region. The guard ring increases the rated voltage of the device without the introduction of a passivation layer.

Abstract: A low voltage planar MOSFET has a polyline width of less than 3.8 microns and a channel (base) region depth of less than 1.5 microns to produce a device having a reduced figure of merit (or product of Q.sub.GD and R.sub.DSON).

Abstract: A surface mount TO-220 package includes leads which are bent within the molded housing and formed prior to molding the housing around the lead frame. A single gauge of frame material is used for both the leads and the main pad area. The bends reduce the height of the package and reduce mechanical stresses in the molded housing.

Abstract: A simple, off-chip circuit and method for endowing high efficiency IGBTs with short-circuit capability, that is essentially transparent to the user. The invention involves adding an external common emitter resistor to reduce the effective gain of an IGBT under short circuit. Under normal operating conditions, the voltage across the resistor is small, such that the modifying effect on the normal operating gate-emitter voltage is almost negligible.

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described and include a layer of amorphous silicon for passivating and terminating the device junctions. The layer of amorphous silicon is deposited atop the metal contact and atop and overlying insulation layer and expose the source pad. A layer of silicon nitride may be deposited atop the layer of amorphous silicon. The layer of amorphous silicon minimizes gate leakage.

Abstract: A method and apparatus for determining the temperature of a discrete power semiconductor from an analog integrated circuit that is copackaged with the power semiconductor on a heat sink, given a knowledge of the thermal capacitances of the power semiconductor and of the analog integrated circuit, the thermal resistance between the power semiconductor and the analog integrated circuit, the thermal resistances between the power semiconductor and the heat sink and between the analog integrated circuit and the heat sink.

Abstract: A surface mount semiconductor package employs locking elements for locking a plastic housing to a metal pad on which a semiconductor device is mounted. The package includes terminals having elongated crushable beads on their side surfaces adjacent the portions of the terminals just outside the plastic housing. The beads are crushed inwardly by a molding tool when it closes to provide a seal which prevents the molding plastic from bleeding out and over the sides of the terminals which extend beyond the housing and which could interfere with solder connection to the terminals.

Abstract: A circuit, for detecting a junction temperature of an insulated gate bipolar transistor (IGBT) which is alternately biased on and off in response to a gate signal, includes a differentiator circuit operable to receive a collector to emitter voltage of the IGBT and produce an output voltage proportional to a rate at which the collector to emitter voltage changes; and a feedback circuit operable to receive the output voltage and alter the gate signal when the output voltage indicates that the rate at which the collector to emitter voltage changes is outside a predetermined limit.

Abstract: A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited.

Abstract: The boundary between the P type silicon base and N.sup.+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.

Abstract: A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.

Abstract: A power converter including a switching transformer having a primary winding and a secondary winding, the secondary winding having first and second voltage nodes across which a winding voltage having a variable duty cycle and phase is impressed; a first synchronous rectifier transistor coupled from the first voltage node to a common node; a second synchronous rectifier transistor coupled from the second voltage node to the common node; and a driver circuit operable to receive the winding voltage and produce first and second drive signals to the first and second synchronous rectifier transistors, respectively, the first and second drive signals leading the phase of the winding voltage.

Abstract: A plurality of semiconductor die, which may be of diverse size and diverse junction pattern, are fixed to a common lead frame and within a common package. The semiconductor die are mounted on respective main pad areas that are laterally spaced from one another and which have respective heat sinks. The heat sinks extend from the boundary of the device package and form external pins that are available for external connection at the same or at different potentials. Isolated pins are also provided. The device package may be used for high and low side chopper circuits, synchronous regulator circuits, single-mode bridges, and the like.

Abstract: A photovoltaic generator device for producing an output sufficient to turn on a MOS-gated device consists of a plurality of planar photogenerator cells connected in series. Each of the photovoltaic generator cells is contained on its own respective insulated tub. The insulated tubs are formed by wafer bonding a device wafer to a handle wafer with a dielectric isolation layer between them. Prior to joining the two wafers, a reflective layer is deposited on the surface of the device wafer to maximize absorption of incident light by the photogenerator cell. The individual tubs are isolated by trenches which enclose each tub and which extend through the reflective and to the dielectric layers between the device and handle wafers. Each tub is formed of an N.sup.- body having a shallow P.sup.+ diffusion. N.sup.+ contact regions are formed in the N.sup.- body and contact strips connect the devices of each of the tubs in series by connecting the P.sup.+ diffusions of one tub to the N.sup.+ contact of an adjacent tub.

Abstract: A power circuit having a reverse battery protection feature, a current sensing feature and a temperature sensing feature employs a MOS gated power semiconductor device or other resistive device in the forward current path of a power stage. An information converting device converts analog information indicative of at least one of the current flowing through the resistive device and a signal from a temperature sensing device into a digital signal for delivery to a microprocessor.

Abstract: A snubber device for a power switch comprising a sensing device coupled in the output circuit of the power switch, the sensing device having a reference input and providing an output indicating if a transient pulse of a magnitude greater than a preset range occurs in the output circuit of the power switch. A further electronic switch is provided having an input coupled to an output of the sensing device and coupled across the power switch, the further electronic switch being turned on by the sensing device in the event the sensing device detects a transient pulse beyond the preset range, thereby completing a shunt circuit across the electronic switch and dissipating the transient pulse.

Abstract: A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5.times.10.sup.12 atoms per centimeter squared and is driven for about 10 hours at 1175.degree. C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through L.sub.S1 and L.sub.S2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances L.sub.S1 and L.sub.S2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the L.sub.S1 and L.sub.S2 inductances. The external, charging capacitor C.sub.b value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 .mu.F, for a given circuit, IGBT and layout combination. The size of the C.sub.VCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, C.sub.VCC is at about ten times the value of the sum of the C.sub.b capacitance in the circuit. The resistance R.sub.b in the bootstrap path is reduced as much as possible, preferably to zero.