Abstract: A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited.
Abstract: A massive heat slug in thermally coupled to the top of an IGBT to act as a local thermal inertia element to absorb and store heat from the die during peak temperature rise and to return heat to the die at reduced die temperature, thereby reducing the ratio of die peak temperature to die average temperature. The device is useful in applications in which the IGBT is called upon to carry current at a range of frequencies which includes very low (eg 3 Hz) frequencies as in a motor control circuit.
Abstract: A method and circuit for driving power transistors arranged in series in a half bridge configuration allowing for excessive negative swing of an output node between the transistors in the half bridge configuration. The series transistors are connected between a first voltage source and a common potential. A second voltage reference source is also provided. A terminal is connected to a common point coupled to anodes of intrinsic diodes of driver circuits for the power transistors. The second voltage source is connected between the common potential and the terminal so as to shift the level of the common point such that the intrinsic diodes will not forward bias due to negative output node transients generated by diode forward recovery and stray inductances. The circuit of the invention can also be incorporated in an integrated circuit including a single chip, e.g., a silicon chip.
Abstract: A metal oxide semiconductor (MOSFET) half bridge module for use in a 42 volt internal combustion engine starter/alternator circuit. The module is a compact, high power handling device which has an extremely low inductance. This low inductance module supports the current and current slew rates necessary to properly operate in an internal combustion engine starter/alternator circuit across a wide temperature range. The module has a thermally conductive base. A plurality of lower circuit boards are adjacently positioned within the base along the same plane. At least one semiconductor device has a first surface, the first surface of the semiconductor device is mounted to one of the plurality of circuit boards. A common terminal has planar portion which is coupled to each of the plurality of lower circuit boards. An upper circuit board is in electrical contact with the plurality of lower circuit boards and includes a connector providing external access for drive signals for the semiconductor device.
Abstract: An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of each of the cells. A second photolithographic step is aligned to a small central area above the source region of each of the cells or strips, the only critical alignment in the process, and is used to define openings in a protective oxide layer which, in turn, masks the etching of depressions in the substrate surface and the formation of a contact region. An isotropic etch undercuts the protective oxide to expose shoulders at the silicon surface of the chip which surround the etched holes. A conductive layer fills the holes and thus contacts the underlying body regions and overlaps the shoulders surrounding the source regions at the silicon surface.
Abstract: A fast recovery diode (FRED) is fabricated by a process using a reduced number of masking steps. The FRED is a vertical conduction device in which P type anode regions are isolated using either LOCOS oxidation or deposited low temperature oxide. The first masking step defines the anode and isolation regions, and a second masking step defines the aluminum contact layer. For devices having a breakdown voltage greater than 800 volts, a third masking step is included which defines the passivated area.
Abstract: The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.
Abstract: A MOSgated trench type power semiconductor device is formed in 4H silicon carbide with the low resistivity direction of the silicon carbide being the direction of current flow in the device drift region. A P type diffusion at the bottom of the U shaped grooves in N− silicon carbide helps prevent breakdown of the gate oxide at the trench bottom edges. The gate oxide may be shaped to increase its thickness at the bottom edges and has a trapezoidal or spherical curvature. The devices may be implemented as depletion mode devices.
Abstract: An ignition circuit for a high intensity discharge (HID) lamp, comprising: first and second series coupled switching transistors connected across upper and lower voltage buses to which a source of DC voltage is connectable, the first switching transistor being connected from the second switching transistor at a common node to the upper voltage bus and the second switching transistor being connected from the common node to the lower voltage bus; a first capacitor connected, at one end, to the common node of the series coupled pair of switching transistors; a first diode having an anode connected to an opposite end of the first capacitor, and a cathode; a second capacitor coupled from the cathode of the first diode to the lower voltage bus; a second diode having an anode coupled to the upper voltage bus, and a cathode connected to the cathode of the first capacitor and the anode of the first diode; a spark gap having opposing ends and being coupled, at one end, to the cathode of the first diode; a pulse transfo
Abstract: A schottky diode is formed of a sintered barrier metal layer which contacts a lightly doped silicon surface. The barrier metal layer is formed of palladium as well as a small quantity of another metal whose choice is determined by the desired value of the barrier height of the resulting schottky diode. A small quantity of platinum is selected to increase the barrier height, and a small quantity of nickel is selected to decrease the barrier height. A contact metal, which may include a tri-metal layer of titanium, nickel and silver, is formed atop the sintered schottky barrier layer. The resulting process also allows for control of reverse hot leakage current.
Abstract: An electronic package for an electronic device includes a substrate. A power transistor die has a lower surface and a upper surface, and the lower surface of the power transistor die is mounted on the substrate. A control circuit for controlling the power transistor is mounted to the upper surface of the power transistor die using an insulating epoxy.
Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.
Abstract: A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.
Abstract: A power module for a motor in which the module is arranged to house both the high power devices needed to drive the phase windings of the motor and the control electronics needed to control the operation of the high power devices. The components are arranged such that the thermal energy generated by the high power devices is directed away from the control electronics for subsequent dissipation. An insulated metal substrate is used as the base of the module for directing the thermal energy. Further, the module components can be easily assembled through the use of solderless resilient connections from the control electronics to the other components in the module. The module employs a base, a power shell coupled to the base, and a circuit board positioned within the internal chamber of the power shell. The power shell has a plurality of walls forming an internal chamber and at least one conductive region. At least one electronic device is mounted to the conductive region.
Abstract: An Adaptable Planar Module (APM) provides a new packaging concept suitable for motor control and other functions. An insulated metal substrate (IMS) supports power semiconductor devices and is formed in an opening in a support base and extends at or below a bottom surface of a base to allow for thermal contact with a heatsink. A circuit board for supporting and interconnecting lower power devices is mounted above and spaced from the support base and has an opening therein which is located above the IMS. The circuit board has bonding pads which are electrically connected to the low power devices. Bonding wires provide an electrical connection between the bonding pad of the printed circuit board and the power devices on the IMS substrate. Integral or procured terminals are also provided for external connections. Additional circuit boards may also be provided in the module and arranged co-planar with or above the first circuit board.
Abstract: A MOSgated device has a plurality of rows of closed cells which each have a laterally enlarged central base area having two narrow oppositely extending base stripes. Each cell in the row is spaced from the adjacent cell in the row, and each cell of one row is nested into the cells of an opposite row such that its enlarged central region is longitudinally located adjacent the space between the cells of the adjacent row. The polysilicon gate is a continuous sheet and permits gate current to spread both longitudinally and laterally. The invention can be carried out with planar and groove technologies.
Abstract: A MOSFET die and a Schottky diode die are each mounted within a device package on a common lead frame pad with their drain and cathode terminals, respectively, connected together at the common pad. The source terminal of the MOS gated device and the anode terminal of the Schottky diode are each electrically connected by wire bonds to an insulated pin, and the gate electrode of the MOS gated device is electrically connected by wire bonds to another pin. A redundant wire connection runs from the source terminal of the MOS gated device to the anode terminal of the Schottky diode reduce the inductance in the anode lead.
Abstract: A power MOSFET die and a logic and protection circuit die are mounted on a common lead frame pad, such as a TO220 lead frame pad. The logic and protection circuit die includes a MOSFET that is connected in parallel with the power MOSFET but which is smaller than the power MOSFET and which dissipates power at a predetermined fraction of that of the power MOSFET. The logic and protection circuit die also includes a temperature sensor that is in close proximity to the MOSFET and determines the temperature of the MOSFET. The die also includes another temperature sensor that is located distant from the MOSFET to determine the temperature of the lead frame. The temperature of the power MOSFET can be determined from the temperature measured by these two sensors and from the ratio of the power dissipated by the two MOSFETs.
Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.
September 28, 1998
Date of Patent:
October 17, 2000
International Rectifier Corp.
Christopher Davis, Chuan Cheah, Daniel M. Kinzer
Abstract: A MOSgated device has a plurality of spaced polysilicon diodes on top of a thin insulation layer atop a MOSgated device die. A constant forward current through the diodes produces a voltage drop which is related to the die temperature. The anode and cathode ends of the diode string are connected to the metal pads on the die surface. A first capacitor connects the calkode terminal of the string to the MOSgated device drain electrode and a second capacitor is connected across the anode and cathode ends of the diode string. Both the anode and cathode are unaffected by noise at the drain electrode. The diode string is located within a narrow strip along the die center and is separated from the MOSFET active area by a very narrow termination region which excludes a metal bus.