Abstract: A process is described for making a superjunction semiconductor device. a large number of symmetrically spaced trenches penetrate the N− epitaxial layer of silicon atop an N+ body to a depth of 35 to 40 microns. The wells have a circular cross-section and a diameter of about 9 microns. The trench walls are implanted by an ion implant beam of boron which is at a slight angle to the axis of the trenches. The wafer is intermittently or continuously rotated about an axis less than 90° to its surface to cause skewing of the implant beam and more uniform distribution of boron ions over the interior surfaces of the trenches.

Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.

Abstract: A contact clip for the aluminum contact of a semiconductor device has a central nickel-iron body, preferably Nilo alloy 42, which is coated on top and bottom by a soft, but high conductivity metal such as gold, silver or copper. The nickel-iron body has a thickness of about 15 mils, and is about the thickness of the silicon die. The conductive layers have a thickness of about 5% to 20% of that of the nickel-iron core.

Abstract: A power MOSFET die and a logic and protection circuit die are mounted on a common lead frame pad, such as a TO220 lead frame pad. The logic and protection circuit die includes a MOSFET that is connected in parallel with the power MOSFET but which is smaller than the power MOSFET and which dissipates power at a predetermined fraction of that of the power MOSFET. The logic and protection circuit die also includes a temperature sensor that is in close proximity to the MOSFET and determines the temperature of the MOSFET. The die also includes another temperature sensor that is located distant from the MOSFET to determine the temperature of the lead frame. The temperature of the power MOSFET can be determined from the temperature measured by these two sensors and from the ratio of the power dissipated by the two MOSFETs.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etched away, under the nitride layer to expose the surface of adjacent P diffusions and the spanning N type silicon surface. All nitride is then removed and a top contact layer of aluminum is applied atop the silicon surface, contacting a P guard ring diffusion; the surface of the P diffusions defining PN junctions; and the top of the N silicon to define a Schottky diode contact.

Abstract: A surface mount TO-220 package includes leads which are bent within the molded housing and formed prior to molding the housing around the lead frame. A single gauge of frame material is used for both the leads and the main pad area. The bends reduce the height of the package and reduce mechanical stresses in the molded housing.

Abstract: A process for forming a true chip scale package comprising the sandwiching of a silicon wafer with a large number of identical die therein between top and bottom metal contact plates of the same size as the wafer. The sandwich is secured together as by soldering, and the die and contact plates are singulated in the form of a final chip scale package. The edge of each chip may have an insulation band formed thereon. Slots may be formed in the top contact to define, with the edge saw cuts, a separate contact area on each top contact.

Abstract: An electronic module is provided using one or more field effect transistors (FETs) arranged on a conductive plate such that the module is capable of switching very high currents while remaining compact and still providing excellent thermal management properties. A plurality of conductive plates are bonded with an insulating material, the insulating material also forms a housing. One or more FETs are arranged inside the housing on one of the plates such that an electrical connection is made between a first region of the FET and the plate. A second FET region is electrically connected to another conductive plate. A circuit board is contained within the housing in which an electrical connection is made between the second region and the circuit board, and between a third FET region and the circuit board.

Abstract: A cutting blade assembly for an ultrasonic wire bonding machine has a replaceable carbide cutting blade so that the entire blade assembly need not be replaced after a given amount of blade wear.

Abstract: A power semiconductor device module has a plurality of spaced thermally supported substrates mounted within coplanar openings in an insulation support shall and electrically insulated from one another by the body of the insulation support shell. Each of the substrates may be a separate metal heatsink or a separate IMS sheet. Each of the substrates may receive one or more semiconductor die. A printed circuit board containing control circuits for the die is mounted above the plane of the substrate and contains openings in registry with each substrate for wire bonding the control circuits to the die. The structure permits the reduction in area of any IMS substrate or permits the elimination of the IMS.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A semiconductor device package is provided which can accommodate currents larger than those of similarly sized standard device packages such as the “TO-247” package. Higher currents are accommodated by allowing a larger semiconductor die to be mounted on the device's lead frame than can be mounted on a similarly sized standard package. An improved mold clamping area is also provided which reduces the area from which damaging moisture can enter the molded package and increases the distance required for moisture to contact the die. Clip arrangements are also provided to mount the device package to a circuit board or heat sink, thereby allowing the increased operating temperatures associated with the increased operating currents to be efficiently dissipated.

Abstract: A power module includes a three-phase inverter circuit. The positive and negative terminals of the module are centrally located on opposing sides of the module to reduce the length of the current path between the terminals. The reduced current path length significantly reduces the inductance and capacitance of the module.

Abstract: A known good die testing apparatus for pre-package testing singulated semiconductor die includes a plurality of test nests for receiving at least one of the singulated semiconductor die, each test nest including first and second portions which are movable away from one another to receive the singulated die, the first portion having a probe card coupled thereto which includes at least one needle for electrically connecting to a first side of the semiconductor die and at least one first edge connector electrically coupled to a respective needle; and at least one test unit in movable communication with respect to the test nests, the test unit being adapted to removably engage the first edge connector of the test nests, the test unit including at least one electrical circuit for performing electrical tests on the semiconductor die.

Abstract: A MOSFET die is mounted onto the bottom surface of a lead frame pad of a lead frame which has increased heat conducting capacity. The pad includes a plurality of at least four integral pins extending therefrom. The lead frame also includes isolated pins which are connected to the MOSFET source and drain using wire bonds. The lead frame and MOSFET are molded in a housing. The pins extend outside the molded housing for external connection, and the pins extending from the lead frame pad provide a path for heat removal from the MOSFET by a heat conduction path formed of the MOSFET drain electrode, the lead frame pad, their interconnection material and the pins.

Abstract: The collector (anode) of a non punch through IGBT formed in a float zone silicon monocrystaline wafer is formed with a DMOS top structure and is thereafter ground at its bottom surface to a less than 250 micron thickness. A shallow P type implant is then made in the bottom surface and the wafer is then heated in vacuum to about 400° C. for about 30 to 60 seconds to remove moisture and other contaminants from the bottom surface. An aluminum layer is then sputtered on the bottom surface, followed by other metals to form the bottom electrode. No activation anneal is necessary to activate the weak collector junction.

Abstract: A switching power converter for producing regulated D.C. power at two or more voltages. First and second regulation circuits including switching elements are connected across the secondary side of a transformer. A control circuit including a phase lock loop provides a first timing signal in leading relation to the AC input, and a delay circuit which provides a second timing circuit in delayed relation to the first timing signal. A logic circuit is responsive to the first and second timing signals to provide drive signals for the switching elements. The regulation circuits each include a first switching element having a power terminal coupled to the secondary winding and another power terminal is coupled to an intermediate node. A second switching element has a power terminal coupled to the intermediate node and another power terminal coupled to a common node. An inductor is coupled from the intermediate node to an output node.

Abstract: A MOSgated device is resistant to both high radiation and SEE environments. The active area of the device is formed of trench devices having a thin gate dielectric on the trench walls and a thicker dielectric on the trench bottoms over the device depletion region. Termination rings formed of ring-shaped trenches containing floating polysilicon plugs surrounds and terminates the device active area.