Abstract: A process for forming a power MOSFET enables the connection a metal gate electrode to the conductive polysilicon gates in the active area without an additional mask step. In the process, a groove is formed in the field oxide during the active area mask step. Conductive polysilicon is then formed over the active area and into the groove. At least one window is formed over the groove along with the mask window for forming the channel and source implant windows, and the polysilicon is etched to the silicon surface in the active area, but a strip is left in the groove. This strip is contacted by gate metal during metal deposition. Thus, gate metal is connected to the polysilicon without an added mask step.

Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

Abstract: A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract: A circuit and method for sensing the inductor current flowing to a load from a switching power supply without using a sense resistor in the path of the inductor current. In a synchronous buck converter topology, the inductor current is derived by sensing the voltage drop across the synchronous MOSFET of the half-bridge and reconstructing the current using a sample and hold technique. A ripple current synthesizer is employed to reconstruct inductor current outside the sample and hold window. The sampled product ILoad×RDSon is used to update the ripple current estimator with dc information every switching cycle. The resulting voltage waveform is directly proportional to the inductor current. The inductor current synthesizer of the present invention can also be used in boost converter, flyback converter and forward converter topologies.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: Semiconductor die are soldered or epoxy bonded to lead frame pads and overhang the pads to reduce thermal differential expansion and contraction stresses applied to the die from the lead frame pad. A plastic housing of standard size is unchanged in dimension, but contains a greater total silicon die area.

Abstract: A dual plane microelectronic relay comprises an input lead frame for carrying an LED an output lead frame carrying a PVG and FETs which are turned on by the output of the PVG in response to its illumination by the LED. Each lead frame is offset in opposite directions so that the lead frame segments carrying the LED and FETs are disposed atop one another while their extending contact pins are coplanar and in line. The PVG and LEDs along the lead frames are accurately located relative to one another by indexed tabs on the side rails of the lead frames. A clear silastic fills the volume between the PVG and LED and the individual units are transfer molded, using an opening in the lead frame rail as a mold gate. A 6 terminal SOP-6 package is formed.

Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an N+ substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a P− drift lower layer. In each case the top of the epitixial layer is N+. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the N+ top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

Abstract: A flexible power assembly (FPA) provides a new packaging concept suitable for motor control and other functions. An insulated metal substrate (IMS) supports power semiconductor devices and is mounted directly on a heatsink, which supports a circuit board that is mounted above and spaced from the top side of the IMS. There are provided devices that are mounted on the circuit board which are electrically connected to the power semiconductor devices. There may be a cavity in the circuit board allowing the top of the IMS to be exposed, and optionally providing access for bonding wires to the top of the circuit. Bonding pads may be provided on the circuit board for electrical connection with the bonding wires. A cover may be optionally provided to enclose a space over the cavity. Potting compound may be contained in the space created by the cavity.

Abstract: A switching power converter for producing regulated D.C. power at two or more voltages. First and second regulation circuits including switching elements are connected across the secondary side of a transformer. A control circuit including a phase lock loop provides a first timing signal in leading relation to the AC input, and a delay circuit which provides a second timing circuit in delayed relation to the first timing signal. A logic circuit is responsive to the first and second timing signals to provide drive signals for the switching elements. The regulation circuits each include a first switching element having a power terminal coupled to the secondary winding and another power terminal is coupled to an intermediate node. A second switching element has a power terminal coupled to the intermediate node and another power terminal coupled to a common node. An inductor is coupled from the intermediate node to an output node.

Abstract: A power MOSFET die with a minimized figure of merit has of a planar stripe MOSFET geometry in which parallel diffused bases (or channels) are formed by implantation and diffusion of impurities through parallel elongated and spaced polysilicon stripes wherein the polysilicon line width is from about 3.2 to 3.4 microns, preferably 3.4 microns; the polyline spacing is from about 1 to 4 microns, preferably 1.5 microns and the diffused bases are spaced by greater than about 0.8 microns. The polysilicon stripes act as masks to the sequential formation of first base stripes, the source stripes and second higher concentration base stripes which are deeper than the first base stripes. Insulation side wall spacers are used to define a contact etch for the source contact. The above design geometry is used for both the forward control MOSFET and the synchronous rectifier MOSFET of a buck converter circuit.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Abstract: A semiconductor device package has a lead frame with four or more die receiving pads. The first pad is large enough to receive two or more of the die, laterally spaced from one another, while the other pads receive at least one die each. The die may be arranged in a single straight path, or in spaced parallel paths. The tops of selected ones of the die are bonded to lead frame elements of adjacent pads to complete bridge type circuits within the package. The die and pads are enclosed by a molded plastic housing and short sections of the pads protrude through the housing wall.

Abstract: An active filter reduces the common mode current in the ground wire of a PWM controlled motor drive circuit. The active filter is, in part, integrated into an integrated circuit chip and contains a buffer amplifier which drives two junction type or MOSFET transistors linearly to divert common mode current from a ground wire and through the transistors. The transistors are connected between positive and negative d-c busses which supply d-c power to a PWM inventor which drives an a-c motor, producing the common mode ground current in its grounded frame. A current transformer monitors the common mode current and its output is coupled to the input of the buffer amplifier to control the transistors. An internal power supply for the amplifiers is formed at the nodes between two current sources and two zener diodes which are connected between the d-c bus conductors. Headroom control circuits are disclosed to insure sufficient headroom voltage for each of the transistors under all input a-c voltage conditions.

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Abstract: A circuit and method for sensing the inductor current flowing to a load from a switching power supply without using a sense resistor in the path of the inductor current. In a synchronous buck converter topology, the inductor current is derived by sensing the voltage drop across the synchronous MOSFET of the half-bridge and reconstructing the current using a sample and hold technique. A ripple current synthesizer is employed to reconstruct inductor current outside the sample and hold window. The sampled product ILoad×RDSon is used to update the ripple current estimator with dc information every switching cycle. The resulting voltage waveform is directly proportional to the inductor current. The inductor current synthesizer of the present invention can also be used in boost converter, flyback converter and forward converter topologies.