Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.

Abstract: A system and method for regulating power flow and limiting inductor current in a bidirectional direct current (DC)-to-DC converter is provided. In one aspect, a feedback circuit is provided to control power flow and/or limit inductor current based on the input/output voltage and/or current conditions in the bidirectional DC-DC converter. During a boost mode of operation, the duty cycle of a low-side switch within the bidirectional DC-DC converter is reduced, based on an analysis of the high-side voltage and positive inductor current. Further, during a buck mode of operation, the duty cycle of the low-side switch is increased, based on an analysis of the low-side voltage and negative inductor current. Moreover, the duty cycle of the low-side switch is adjusted, such that, the high-side voltage, low-side voltage and inductor current (in both directions) do not exceed preset threshold and the bidirectional DC-DC converter returns to a steady state.

Abstract: Signals propagating from an aggressor communication channel can cause detrimental interference in a victim communication channel. One or more noise cancellers can generate an interference compensation signal to suppress or cancel the interference based on one or more settings. A controller can execute algorithms to find preferred settings for the noise canceller(s). The controller can use a feedback signal (e.g., receive signal quality indicator) received from a victim receiver during the execution of the algorithm(s) to find the preferred settings. One exemplary algorithm includes sequentially evaluating the feedback resulting from a predetermined list of settings. Another algorithm includes determining whether to move from one setting to the next based on the feedback values for both settings. Yet another algorithm includes evaluating a number of sample settings to determine which of the sample settings result in a better feedback value and searching around that sample setting for a preferred setting.

Abstract: A voltage regulator generates a regulated output voltage responsive to an input voltage and drive control signals. An error amplifier generates an error voltage signal responsive to the regulated output voltage and a reference voltage. A PWM modulator generates a PWM control signal responsive to the error voltage signal, a ramp voltage and an inverse of the reference voltage. Control circuitry within the PWM modulator maintains the error voltage signal applied to the PWM modulator at substantially a same DC voltage level over the reference voltage operating range and maintains the error voltage signal above a minimum value of the ramp voltage. Driver circuitry generates the drive control signals responsive to the PWM control signal.

Abstract: Systems and methods for managing process and temperature variations for on-chip sense resistors are disclosed. The system includes a circuit that can leverage a linear gm circuit in order to provide linear gains (positive gains and/or negative gains). The linearity of the circuit enables compensation for temperature and process variations across an entire range of current (positive to negative). A control signal is generated by using a linear gm amplifier and a replica resistor, which is substantially similar to the on chip resistor. The control signal is used to control the gain of a disparate linear gm amplifier within a compensation circuit, which provides an offset voltage to compensate for the variation in resistance of the on chip resistor.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: An auto-compensation method for compensating power regulators configured to generate a regulated output voltage. Auto-compensation may be performed dynamically by determining various coefficients of a compensation function used in compensating the power regulator, based on assumptions about the structure of the regulator and corresponding filters. The method may be used to determine at least the DC loop gain and the position of the compensation zeros, without requiring any prior knowledge of the values of the various components of the system. Furthermore, the selection of the compensation parameters (loop gain, position of zeroes) may be based on measurement of various state variables of the actual power converter, and adjustment of the various coefficients of the compensation function according to the measurements. Since no power-plant model of the power regulator is used, inaccuracies that would be inherent using any method that employs a model of the system instead of the system itself may be eliminated.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Abstract: A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode.

Abstract: A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern.

Abstract: Hysteretic performance with fixed frequency may be achieved in controlling a power/voltage regulator, by adapting fixed frequency PWM (Pulse Width Modulation) to current-mode hysteretic control. In steady state, the current waveform may be inferred without having to measure the current. In current-mode control, the current may be adjusted proportional to the error voltage. The change in load current may be related to the change in duty-cycle, and the change in duty-cycle may be related to the error voltage, with the change in duty-cycle expressed as a function of the error voltage, to establish current-mode control. This current-mode control may be adapted to perform current-mode hysteretic, if instead of duty-cycle, the same duty-cycle or current shift was effected by a change in phase. A fraction of ripple current (Forc) may be defined as a specified fraction of the peak-to-peak ripple current, establishing a linear relationship between the Forc and the ripple current.

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract: Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.

Abstract: An AC to DC converter for converting an AC input voltage to a regulated DC output voltage using a Z-type converter and rectified switches. The Z-type converter includes first and second inductors, a capacitor, two rectified switches and a load device coupled in a cross-coupled configuration. The Z-type converter may be configured according to a Z-source or a quasi-Z-source rectifier network. The AC input voltage is applied to an input and the DC output voltage is developed across the load device. Each rectified switch may be configured as a series-coupled diode and electronic switch or as a dual gate GaN device with a shorted gate. A control network monitors the DC output voltage and develops a control signal for controlling the first and second rectified switches to regulate the DC output voltage. The control network may control the rectified switches based on duty cycle control or current mode control.

Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.

Abstract: Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM3, IM5, IM7, IM9, etc.) generated by the power amplifier. The linearizers can obtain samples of signals output by the power amplifier and process the samples to produce a compensation signal that is applied onto or into a transmission path leading to the power amplifier's input. The compensation signal is generated such that when amplified by the power amplifier, the amplified compensation signal cancels or reduces at least a portion of the non-linearity components produced by the power amplifier. A controller can improve the correction of the non-linearity components by executing one or more calibration algorithms and/or one or more tuning algorithms and adjusting settings of the linearizer based on the results of the algorithm(s).

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.

Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal.