Abstract: A multiphase DC-DC converter including at least one conversion path, multiple switch capacitance networks, and a multiphase switch controller. Each conversion path includes first and second intermediate nodes. Each switch capacitance network includes a capacitance coupled in parallel with an electronic switch and is coupled to one of the intermediate nodes. The switch controller controls the switch capacitance networks using zero voltage switching. Multiple phases may be implemented as multiple conversion paths each having first and second intermediate nodes coupled to first and second switch capacitance networks, respectively. A single conversion path may be provided with multiple switch capacitance networks coupled to each intermediate node for multiple phases. Alternatively, a common front end with a first intermediate node is coupled to one or more switch capacitance networks followed by multiple back-end networks coupled in parallel for multiple phases.

Abstract: A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern.

Abstract: A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold level. A positive charge pump embodiment charges the output to twice the positive supply voltage up to no more than a limit level. A negative charge pump embodiment charges the output to the same magnitude with opposite polarity as the positive supply voltage, and decreases the output magnitude if the positive supply voltage is above the threshold level. A Zener diode and controlled current mirror may be used for control.

Abstract: A power supply including an AC input, a filter, a full wave rectifier, a converter, a second rectifier, and a bias system. The filter includes at least one differential capacitor coupled to the AC input. The full wave rectifier develops a DC bus voltage on a DC bus node. The converter includes a controller and operates to convert the DC bus voltage to a regulated output voltage. The second rectifier is coupled to the AC input for developing a DC bias voltage on a DC bias node. The bias system is coupled between the DC bias node and a reference node and provides at least one start-up voltage to the controller, such as a supply voltage or a sense voltage or the like. The bias circuit includes at least one current discharge path for discharging each differential capacitor within a predetermined time period when AC line voltage is removed.

Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.

Abstract: A phase current sharing network for a current mode multiphase switching regulator. The multiphase switching regulator includes switching networks for developing phase currents of switching phase networks controlled by pulse control signals for converting an input voltage to an output voltage. The regulator develops the pulse control signals based on current control values and at least one trigger value. The phase current sharing network includes conversion networks and a phase current combining network. Each conversion network provides a phase current value based on a corresponding phase current, such as by directly or indirectly measuring real current or by synthetically developing the phase current value. The phase current combining network develops an average phase current value based on the phase current values, and subtracts the average phase current value from each phase current value to provide the current control values used to control the switching networks.

Abstract: Circuitry and methodology for tracking the maximum power point (MPP) of a solar panel is disclosed. The voltage and current generated by the solar panel are monitored and used to generate a pulse signal for charging a capacitor. The changes in the voltage and current generated by the solar panel are also monitored, and that information is used to generate a pulse signal for discharging the capacitor. The charging and the discharging pulse signals are used to charge and discharge the capacitor. A reference signal indicative of the charge level of the capacitor is generated. As the current and voltage generated by the solar panel approach the maximum power point (MPP), the frequency of the discharging pulse signal becomes progressively higher, so that the capacitor charging occurs in progressively smaller increments. When the MPP is reached, the reference signal level becomes steady because the charge level of the capacitor becomes steady.

Abstract: The various embodiments may include a power supply having a first loop in communication with a power stage of the power supply. A second loop in communication with the first loop may generate a negative reactance value that increases a power factor for the power supply to approximately one. A power supply may also include a rectifier coupleable to an input supply. A power factor compensation circuit coupled to the rectifier may generate a negative reactance. The negative reactance may reduce a phase angle between a current and a voltage provided to the input supply. A method may include sensing an output of a power supply, and adjusting the sensed value. The adjusted value may be compared to a reference value to generate an error value. The error value and a negative reactance value may be combined and the result may be provided to the power supply.

Abstract: Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.

Abstract: Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs.

Abstract: Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected.

Abstract: An electronic system is disclosed, which includes a connector unit to communicate data with a host system, an electronic circuit to store the data, and a switch to convey the data to and from the electronic circuit via the connector unit. The switch includes a negative voltage protection unit coupled to the connector unit, and a transistor switch coupled to the negative voltage protection unit, the connector unit, and the electronic circuit. The negative voltage protection unit forces the transistor switch off if a negative voltage is detected.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.

Abstract: Provided herein are circuits, systems and methods that monitor for way out of balance (WOB) conditions within a multi-phase DC-DC converter, and adjust a balance between currents through channels of the DC-DC converter, in dependence on detected WOB conditions.

Abstract: A voltage regulator includes an upper switching transistor connected between an input voltage node and a phase node. A lower switching transistor is connected between the phase node and ground. An output filter is connected between the phase node and an output voltage node. A PWM control circuit generates an PWM control signal responsive to a feedback voltage. An upper gate control circuit controls operation of the upper switching transistor responsive to the PWM control signal. A lower gate control circuit controls operation of the lower switching transistor responsive to the PWM control signal and a ramp voltage signal. The lower gate control circuit linearly increases a lower gate control signal from 0 to (1-D), where D=the duty cycle, to transition the voltage regulator for diode emulation mode of operation to synchronous mode of operation responsive to a first pulse in the PWM control signal.

Abstract: Systems and methods for determining an unknown QPSK or QAM constellation from a set of possible received constellations are described. One method utilizes a histogram of the power of the signal after inter-symbol-interference has been minimized with a modified constant modulus algorithm equalizer. The constellation may be determined before carrier frequency and phase has been fully recovered. An unknown QPSK or QAM constellation may be identified before or after equalization using disclosed methods for analyzing an output power histogram.

Abstract: A system, voltage supply circuit, control unit for a voltage supply circuit, and method of controlling a voltage supply circuit are disclosed. For example, a system is disclosed that comprises at least one electronic circuit and a voltage supply unit coupled to an input of the at least one electronic circuit. The voltage supply unit includes a power unit to supply a voltage to the at least one electronic circuit and a control unit to control an operating mode of the power unit, an output of the control unit coupled to an input of the power unit. The control unit includes a mode selector to select the operating mode of the power unit, coupled to at least a first output of the power unit, an amplifier coupled to the at least a first output of the power unit, a compensation circuit, and a first switching unit coupled to the mode selector and the compensation circuit, to couple the compensation circuit to the amplifier if a selected operating mode of the power unit is a first mode.

Abstract: A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies