Abstract: Described herein are light sensors that primarily respond to visible light while suppressing infrared light. Also described herein are systems the incorporate such light sensors. Such a system can include a display, a light source to backlight the display and a controller to control the brightness of the light source based on feedback received from such light sensors. Described herein are also methods for controlling backlighting.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.

Abstract: Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

Abstract: In accordance with an embodiment of the present invention, a bandgap voltage reference circuit includes a group of X current sources, a plurality of circuit branches, and a plurality of switches. Each of the X current sources (where X?3) produces a corresponding current that is substantially equal to the currents produced by the other current sources within the group. The plurality of circuit branches of the bandgap voltage reference circuit are collectively used to produce a bandgap voltage output (VGO). Each of the plurality of circuit branches receives at least one of the currents not received by the other circuit branches. The plurality of switches (e.g., controlled by a controller) selectively change over time which of the currents produced by the current sources are received by which of the plurality of circuit branches of the bandgap voltage reference circuit.

Abstract: Systems and methods for implementing over-current protection include reducing a clip level while an over-current condition is being detected. Once the over-current condition is no longer detected, the clip level is maintained for a specified period before allowing the clip level to be increased. In an embodiment, the specified period, for which the clip level is maintained before the clip level is allowed to be increased, starts when the over-current condition is no longer detected, and ends when each of N immediately preceding sample(s) of the audio signal are not clipped to the clip level, where N is an integer ?1. After an over-current condition is no longer detected, and after the clip level has been maintained for the specified period, the clip level can be increased if an over-current condition is not detected for a sample and the clip level is below a specified maximum clip level.

Abstract: Systems and methods for determining an unknown QPSK or QAM constellation from a set of possible received constellations are described. One method utilizes a histogram of the power of the signal after inter-symbol-interference has been minimized with a modified constant modulus algorithm equalizer. The constellation may be determined before carrier frequency and phase has been fully recovered. An unknown QPSK or QAM constellation may be identified before or after equalization using disclosed methods for analyzing an output power histogram.

Abstract: Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed.

Abstract: Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM3, IM5, IM7, IM9, etc.) generated by the power amplifier. The linearizers can obtain samples of signals output by the power amplifier and process the samples to produce a canceling signal that is applied onto or into an output of the power amplifier. The canceling signal is generated such that when applied to the output of the power amplifier, the canceling signal cancels or reduces at least a portion of the non-linearity components produced by the power amplifier. A controller can improve the correction of the non-linearity components by executing one or more tuning algorithms and adjusting settings of the linearizer based on the results of the algorithm(s).

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed.

Abstract: Techniques for calibrating non-linearities of ADCs are described, which can be applied whether or not the non-linearities change with frequency. When the non-linearities do not change (are static), the frequency of a calibrating signal is first estimated coarsely in a calibration mode, then a fine estimate is determined using the coarse estimate. These estimates are then used to predict the sinusoidal signal using a linear predictor. A Look Up Table (LUT) containing corrections to the ADC is derived from this result. The LUT is then used in a normal operating mode to correct the output of the ADC. In a case where the characteristics of the non-linearities of the input signal are dynamic and thus change with frequency, a frequency spectrum of interest is broken into several regions. In each of these regions, a frequency is identified and used as a calibrating signal to generate the corresponding LUT.

Abstract: A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.

Abstract: A circuit comprises a plurality of segments and a clamp circuit. Each of the plurality of segments comprises a bond pad coupled to a multi-bonded pin via a respective bond wire and a conductor coupling the bond pad to a respective internal connection. The bond pad from each of the plurality of segments is coupled to the same multi-bonded pin. The clamp circuit comprises a plurality of input pins and a plurality of clamp transistors. Each input pin is coupled to the bond pad of a respective one of the plurality of segments via the respective conductor. Each clamp transistor is coupled to a respective one of the input pins, wherein each of the plurality of clamp transistors is configured to prevent a voltage on the respective conductor from exceeding a respective voltage limit.

Abstract: A circuit for generating an output voltage to a top node of a plurality of LED strings. The circuit includes an inductor having a load current flowing therethrough and a switching transistor responsive to a switching control signal. An integrator generates a compensation voltage responsive to a voltage at a bottom node of the LED string and a reference voltage. Circuitry for combining an offset with the compensation voltage is responsive to the compensation voltage and the load current through the inductor. The offset is generated only during a step load change of the load current and substantially reduces voltage transients from the compensation voltage and the output voltage. A summation circuit sums the compensation voltage including the offset with at least the voltage at the bottom node of the LED string to generate a first control signal. A latch generates the switching control signal responsive to the first control signal and a leading edge blanking signal.

Abstract: An antenna module with a detector and an associated canceller is disclosed. The detector may also detect interference and spurs. In one embodiment, an antenna module can include: an antenna configured to receive an electromagnetic signal in a signal path; an amplifier configured to amplify the received electromagnetic signal, and to provide the amplified signal at a first node; a filter configured to receive the amplified signal from the first node, and to provide a filtered signal output therefrom; and a noise canceller and a detector integrated in the signal path at the first node.

Abstract: An inrush current control circuit selectively short-circuit bypasses an inrush current limiting resistor (R1) of a power supply that includes a switching transistor (Q1) having a control terminal (gate or base) driven in dependence on a pulse width modulated (PWM) drive signal. The inrush current control circuit includes a bypass transistor (Q3), a first resistor (R3), a capacitor (C2), a second resistor (R2) and a diode (D3), wherein an anode terminal of the diode (D3) is connected to one of the terminals of the switching transistor (Q1) of the power supply.

Abstract: A power supply including a converter, a capacitance, and a hiccup control module. The converter converts an input voltage to both an output voltage and a preliminary standby voltage when in its active state. The capacitance stores the preliminary standby voltage which is charged to an upper voltage level when the converter is in its active state and which is discharged to a lower voltage level when the converter is in its inactive state. During the standby mode, the hiccup control module operates the converter in hiccup mode by toggling between placing the converter into its inactive state when the preliminary standby voltage is charged to the upper voltage level and placing the converter into its active state when the preliminary standby voltage is discharged to the lower voltage level. The hiccup mode of the power supply eliminates a need for a separate standby converter.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.