Abstract: A lead frame having a die thereon connects a conductive area on the die to a lead frame contact using a conductive clip that includes a structural portion that is received with a recess-like “tub” formed in the lead frame contact. The end of the clip received in the tub is held in place during subsequent handling by a solder paste deposit until the clip and leadframe undergo solder reflow to effect a reliable electrical connection. The effective surface area between one side of the clip and the other side of the clip within the tub is different so that the surface tension of the liquefied solder formed during the solder reflow step will “draw” the clip into a preferred alignment against a “stop” surface.

Abstract: A clip interconnect comprises a columnar part, a bridge part, and a locking feature. The bridge part has a plurality of sides. The columnar part and the bridge part are configured to form an angle at an interface between the columnar part and the bridge part. The locking feature is located in at least one of the plurality of sides of the bridge part. The locking feature comprises an alternating pattern of teeth and valleys.

Abstract: Circuits, methods, and apparatus that reduce the power required to drive transistors in switching power supply regulators under various load conditions. One example provides a power supply regulator having multiple parallel transistors in order to reduce series on resistance. When the regulator is lightly loaded, a reduced number of devices are driven by the regulator. That is, one or more devices are not driven, rather their gates are held at a voltage such that the devices remain in the off or non-conductive state. When the regulator is more heavily loaded, more or all of the devices are driven.

Abstract: A single-cycle charge regulator (SCCR) may be used in operating a power converter at a constant frequency without requiring compensation. The SCCR may include a first control loop to generate an error value based on the output voltage of the power converter and a reference voltage, and to generate a first control value based on the error value to control steady-state behavior of the output of the power converter. A second control loop may generate a second control value based on the error value, to regulate response of the power converter to a transient deviation on the output voltage.

Abstract: A communication system comprising a first and second transceiver is provided. The first transceiver has a first and second port coupled to a communication medium, wherein a first differential capacitor couples the first and second ports together. The second transceiver has a third and fourth port each AC coupled to the communication medium, wherein a second differential capacitor couples the third and fourth ports together.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A circuit, device, and method for controlling a buck-boost circuit includes a bootstrap capacitor voltage regulator circuit and a comparator circuit. The bootstrap capacitor voltage regulator circuit is electrically coupled to a buck-mode bootstrap capacitor of the buck-boost converter and to a boost-mode bootstrap capacitor of the buck-boost converter. The comparator circuit is configured to control the bootstrap capacitor voltage regulator circuit to maintain a voltage of the bootstrap capacitors above a reference threshold voltage by transferring an amount energy from one of the bootstrap capacitors to the other bootstrap capacitors based on the particular mode of operation of the buck-boost converter.

Abstract: An embodiment of a power supply includes an input node that receives an input voltage, an output node on which a regulated output voltage is provided, an odd number of magnetically coupled phase paths each coupled between the input and output nodes, and a first magnetically uncoupled phase path coupled between the input and output nodes. Such a power supply can improve its efficiency by activating different combinations of the coupled and uncoupled phase paths depending on the load conditions. For example, the power supply may activate only an uncoupled phase path during light-load conditions, may activate only coupled phase paths during moderate-load conditions, and may activate both coupled and uncoupled phase paths during heavy-load conditions and during a step-up load transient.

Abstract: A converter system including a cascade boost converter and inverting buck converter and controller for converting a rectified AC voltage to a DC output current. The system uses inductors and is configured to use a common reference voltage. The controller is configured to control switching of the converters in an independent manner to decouple operation from each other. For example, control pulses for the boost converter may be wider than pulses for the buck converter. The controller may control the boost converter based on constant on-time control and may control the inverting buck converter based on peak current control. The rectified AC voltage may be an AC conductive angle modulated voltage, where the controller may inhibit switching of the inverted buck converter at a dimming frequency having a duty cycle based on a phase angle of the AC conductive angle modulated voltage.

Abstract: INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>?1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>?1. Such stored first and second sets are thereafter used when performing digital to analog conversions.

Abstract: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Abstract: A method of operating a regulator controller IC for performing intermittent diode braking for controlling a multiple phase voltage regulator. The method includes receiving at least one signal for detecting repetitive load transients, determining a rate of the repetitive load transients, generating diode braking control signals, each for applying diode braking to a corresponding one of multiple phases for at least one load transient when the repetitive load transients are below a first rate, and controlling the diode braking control signals to drop application of diode braking of at least one phase for at least one load transient when the repetitive load transients are at least the first rate. The method may include rotating the application of diode braking among the phases during successive applications of diode braking. The method may include dropping an increased number of phases for diode braking as the rate of repetitive load transients is increased.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. The compensating is selectively locked and reset in response to specific conditions being detected, e.g., a locking condition and a reset condition.

Abstract: A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.

Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.

Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: A regulator controller which controls conversion of an input voltage to an output voltage, including a switching regulator, a low dropout (LDO) regulator, and a mode controller. The switching regulator develops a pulse control signal to regulate the output voltage when enabled. The LDO regulator also regulates the output voltage when enabled. The mode controller enables or disables the switching regulator and the LDO regulator based on a load condition. The switching regulator is enabled and the LDO regulator is disabled during normal operation. The LDO regulator is enabled when the low load condition is detected, such as a skipped pulse on the pulse control signal. The switching regulator is disabled when the pulse control signal reaches a minimum level. The LDO regulator is disabled and the switching regulator is re-enabled based on threshold conditions of the current output of the LDO regulator.

Abstract: An EMI reduction network for a converter, the converter including upper and lower power switches provided between an input voltage node and a reference node. An inductance is coupled between the input voltage node and the upper switch at a first node, a capacitance and an auxiliary power switch are coupled in series between the first and reference nodes, and a controller is provided to control switching. The controller switches the upper switch based on a PWM signal. The controller keeps the lower switch turned on until the phase node goes positive while the upper switch is on. The controller turns the auxiliary switch on after the lower power switch is turned off and turns the auxiliary switch off after the upper power switch is turned off. The lower and auxiliary switches may be zero voltage switched, and the upper switch may be zero current switched.

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract: A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.