Abstract: Systems and methods for operating cameras are described. An image signal received from an image sensor can be processed as a plurality of video signals representative of the image signal. An encoder may combine baseband and digital video signals in an output signal for transmission over a cable. The video signals may include substantially isochronous baseband and digital video signals. The baseband video signal can comprise a standard definition analog video signal and the digital video signal may be modulated before combining with the baseband video signal and/or transmitting wirelessly. The digital video signal may be a compressed high definition digital video signal. A decoder demodulates an upstream signal to obtain a control signal for controlling the position and orientation of the camera and content of the baseband and digital video signals.

Abstract: A method of providing threshold voltage monitoring and control in synchronous power converters is provided. The method includes establishing a threshold voltage level for at least one of a gate drive voltage for an upper and a lower power switch in a synchronous power converter, each threshold voltage level controlling a switching delay time for one of the upper and lower power switches. The method further includes detecting body diode conduction levels for at least one of the upper and lower power switches and adjusting the threshold voltage level for at least one of the upper and lower power switches, based on the detected body diode conduction levels, to fine-tune a body diode conduction time around an equilibrium for the at least one of the upper and lower power switches.

Abstract: A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage.

Abstract: An embodiment of a charger may include an input, at least one switch having a first node coupled to a reference voltage, a current sensor coupled between the input and a second node of the at least one switch, an output coupled to a third node of the at least one switch, and a charge controller coupled to the input to determine an input voltage, to the current sensor to determine an input current and to control inputs of the at least one switch. The at least one switch may be responsive to control signals supplied by the charge controller to the control inputs thereof to control voltage and current at the output of the charger. The charge controller may be responsive to the input voltage and the input current to produce the control signals in a manner that maximizes electrical power drawn at the input.

Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.

Abstract: A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A DC/DC converter comprising voltage conversion circuitry for generating a regulated output voltage responsive to an input current and at least one switching control signal. A current control loop generates the at least one switching control signal to limit an input current responsive to the input current, a reference voltage and a slope signal injected with the reference voltage.

Abstract: A multi channel LED driver comprises a plurality of LED strings. Each of the plurality of LED strings are associated with a separate channel. A voltage regulator generates an output voltage to the plurality of LED strings responsive to an input voltage and a PWM control signal. First control logic generates the PWM control signal responsive to a voltage at a bottom of each of the plurality of LED strings. A plurality of dimming circuitries, each connected to one of the bottoms of the plurality of LED strings, control a light intensity in each of the plurality of LED strings responsive to dimming control signals. Second control logic generates the dimming control signals responsive to forward currents monitored through each of the plurality of LED strings and dimming data.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.

Abstract: An EMI reduction network for a converter, the converter including upper and lower power switches provided between an input voltage node and a reference node. An inductance is coupled between the input voltage node and the upper switch at a first node, a capacitance and an auxiliary power switch are coupled in series between the first and reference nodes, and a controller is provided to control switching. The controller switches the upper switch based on a PWM signal. The controller keeps the lower switch turned on until the phase node goes positive while the upper switch is on. The controller turns the auxiliary switch on after the lower power switch is turned off and turns the auxiliary switch off after the upper power switch is turned off The lower and auxiliary switches may be zero voltage switched, and the upper switch may be zero current switched.

Abstract: A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.

Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.

Abstract: A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract: A switch multiplexer device comprises a plurality of analog switches, and an embedded digital sequencer in operative communication with the analog switches. The embedded digital sequencer including a plurality of sequence control registers. The embedded digital sequencer is configured to transmit control information to the analog switches, with the control information including single or extended control information. The extended control information is employed to pre-load operational information for switch configuration updates when single control operations are conducted. In one embodiment, the switch multiplexer device includes a bitwise manipulator and a data array storage, which are in operative communication with the analog switches and one or more of the sequence control registers.

Abstract: An LED driver controller comprises a voltage regulator for controlling an output voltage to a top of a plurality of LED strings responsive to at least a reference voltage. A plurality of first circuitries each associated with a node at a bottom of each of the plurality of LED strings compares a voltage at the bottom of each of the plurality of LED strings with a high reference voltage and a low reference voltage. Control logic generates a first control signal when the voltage at the bottom of each node of the plurality of LED strings exceeds the high reference voltage and generates a second control signal when the voltage at least one of node of the plurality of LED strings falls below the low reference voltage. Second circuitry responsive to the first control signal and the second control signal generates the reference voltage.