Abstract: A voltage regulator includes an upper switching transistor connected between an input voltage node and a phase node. A lower switching transistor is connected between the phase node and ground. An output filter is connected between the phase node and an output voltage node. A PWM control circuit generates an PWM control signal responsive to a feedback voltage. An upper gate control circuit controls operation of the upper switching transistor responsive to the PWM control signal. A lower gate control circuit controls operation of the lower switching transistor responsive to the PWM control signal and a ramp voltage signal. The lower gate control circuit linearly increases a lower gate control signal from 0 to (1-D), where D=the duty cycle, to transition the voltage regulator for diode emulation mode of operation to synchronous mode of operation responsive to a first pulse in the PWM control signal.

Abstract: A system, voltage supply circuit, control unit for a voltage supply circuit, and method of controlling a voltage supply circuit are disclosed. For example, a system is disclosed that comprises at least one electronic circuit and a voltage supply unit coupled to an input of the at least one electronic circuit. The voltage supply unit includes a power unit to supply a voltage to the at least one electronic circuit and a control unit to control an operating mode of the power unit, an output of the control unit coupled to an input of the power unit. The control unit includes a mode selector to select the operating mode of the power unit, coupled to at least a first output of the power unit, an amplifier coupled to the at least a first output of the power unit, a compensation circuit, and a first switching unit coupled to the mode selector and the compensation circuit, to couple the compensation circuit to the amplifier if a selected operating mode of the power unit is a first mode.

Abstract: Systems and methods for determining an unknown QPSK or QAM constellation from a set of possible received constellations are described. One method utilizes a histogram of the power of the signal after inter-symbol-interference has been minimized with a modified constant modulus algorithm equalizer. The constellation may be determined before carrier frequency and phase has been fully recovered. An unknown QPSK or QAM constellation may be identified before or after equalization using disclosed methods for analyzing an output power histogram.

Abstract: A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.

Abstract: A novel framing method for a variable net bit rate digital communications system that utilizes a set of different QAM constellations and punctured trellis code combinations, each combination designated as a mode. This frame structure has a variable integral number of QAM symbols per frame depending on the selected mode, but the number of bytes and Reed-Solomon packets per frame is constant. This is achieved even though the number of data bits per QAM symbol for some modes is fractional. Also the number of trellis coder puncture pattern cycles per frame is an integer for all modes. This arrangement simplifies the synchronization of receiver processing blocks such as the Viterbi decoder, de-randomizer, byte de-interleaver, and Reed-Solomon decoder.

Abstract: The DC/DC voltage converter comprises at least one switching transistor. An inductor is connected to the at least one switching transistor. A pulse width modulation circuit generates control signals to at least one switching transistor responsive to a current control signal. A current sensor connected in parallel with the inductor senses current passing through the inductor. The sensor comprises a resistor and an NTC capacitor connected in series with the resistor. Circuitry for monitoring the voltage across the NTC capacitor generates the current control signal responsive to the monitored voltage.

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract: An embodiment of a power supply includes an input node that receives an input voltage, an output node on which a regulated output voltage is provided, an odd number of magnetically coupled phase paths each coupled between the input and output nodes, and a first magnetically uncoupled phase path coupled between the input and output nodes. Such a power supply can improve its efficiency by activating different combinations of the coupled and uncoupled phase paths depending on the load conditions. For example, the power supply may activate only an uncoupled phase path during light-load conditions, may activate only coupled phase paths during moderate-load conditions, and may activate both coupled and uncoupled phase paths during heavy-load conditions and during a step-up load transient.

Abstract: In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode.

Abstract: An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

Abstract: An integrated circuit is configured to be coupled to a current sensing element and a set resistor having a resistance Rset. The integrated circuit comprises a sense resistor having a resistance Rsense. The sense resistor is coupled to an input of the integrated circuit such that a first sensed current from the current sensing element flows through the sense resistor. The integrated circuit also comprises a reference resistor having a resistance Rreference which is a fixed multiple of Rsense; and circuitry configured to produce an output current such that the value of the output current is proportional to a value of Rset and a fixed ratio between Rsense and Rreference.

Abstract: Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed.

Abstract: Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM3, IM5, IM7, IM9, etc.) generated by the power amplifier. The linearizers can obtain samples of signals output by the power amplifier and process the samples to produce a canceling signal that is applied onto or into an output of the power amplifier. The canceling signal is generated such that when applied to the output of the power amplifier, the canceling signal cancels or reduces at least a portion of the non-linearity components produced by the power amplifier. A controller can improve the correction of the non-linearity components by executing one or more tuning algorithms and adjusting settings of the linearizer based on the results of the algorithm(s).

Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: Described herein are light emitting element driver integrated circuits (ICs), methods for use with light emitting element driver ICs, and projector systems that include a light emitting element driver IC. A light emitting element driver IC receives a color data word from the video processor IC. Starting with the color data word received from the video processor IC, the light emitting element driver IC performs a gamma expansion function to thereby produce a gamma expanded digital or analog signal. Additionally, the light emitting element driver IC outputs, in dependence on the generated gamma expanded digital or analog signal, a gamma expanded analog drive signal for driving the light emitting element.

Abstract: A method for transmitting data on a data line of a two-wire bus wherein the bus includes a data line and a clock line includes the step of pulling the data line of the two-wire bus low to define a start condition. Next, a first group of fixed data bits enabling a slave device to determine a clock signal for an address portion of a transmission of data are transmitted between a master device and the slave device. An address of the slave device is transmitted from the master device in a second group of data bits. A third group of fixed data bits enabling the slave device to determine the clock signal for a data portion of the transmission of data between the master device and the slave device are transmitted from the master device to the slave device.

Abstract: An embodiment of a power-supply controller includes a signal combiner and a control circuit. The signal combiner is operable to generate a combined feedback signal from sense and output feedback signals that are respectively derived from a sense signal and a regulated output signal, and the signal combiner is operable to receive the sense signal from a sense circuit that is operable to generate the sense signal while a current is flowing through an inductor and while a switch that is disposed between the inductor and an input voltage has a first state. The sense signal generated by the sense circuit is related to the current, and the switch and the inductor are operable to generate the regulated output signal. The control circuit is coupled to the signal combiner and is operable to cause the switch to have a second state for a predetermined time in response to the combined feedback signal having a predetermined relationship to a reference signal.

Abstract: A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.