Abstract: An authentication process for authenticating a battery to a cellular telephone includes the step of receiving a challenge from the cellular telephone at the battery over a single wire conductor. In response to the challenge, the seed values are retrieved from the memory and a response is generated based upon the challenge and the seed values. The response is transmitted back to the cellular telephone from the battery over the single conductor so that a comparison with a similar response generated by the cellular telephone may be made.
Abstract: A pulse width modulation (PWM) modulator for a multiphase power converter and related adaptive firing order (AFO) method includes a multiphase leading edge generator having pulse generating circuitry associated with each of the regulator phases, wherein the pulse generating circuitry generates phase pulses associated with each of the phases. An adaptive firing order (AFO) controller having circuitry including a mixer receives and sums the phase pulses into a summing signal and uses the summing signal to generate a series of turn-on pulses therefrom. A multiphase PWM generator has inputs coupled to an output of the AFO controller coupled to receive the series of turn-on pulses, the multiphase PWM generator having circuitry for generating said PWM signals therefrom. An adaptive firing order (AFO) controlled multi-phase power converter includes a plurality of parallel connected regulator phases controlled by respective pulse width modulation (PWM) signals provided by the PWM modulator.
Type:
Grant
Filed:
March 30, 2007
Date of Patent:
September 22, 2009
Assignee:
Intersil Americas Inc.
Inventors:
Weihong Qui, Shangyang Xiao, Robert H. Isham
Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Type:
Grant
Filed:
December 6, 2007
Date of Patent:
September 22, 2009
Assignee:
Intersil Americas Inc.
Inventors:
Gustavo James Mehas, Sandeep Agarwal, Jayant Vivrekar, Xiaole Chen
Abstract: A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (VOUT) of the converter, wherein a load current flows through the inductor. VOUT is fed back through a network including a feedback resistor (RFB) to an inverting input of the error amplifier. A circuit for sensing the load current includes a first operational amplifier, a sense resistor on the chip having resistance RSENSE coupled to an inverting input of the first amplifier; wherein a sense current related to the load current flows through the sense resistor, a dependent current source provides an output current to supply the sense current. A reference resistor is disposed on the chip having a resistance RREFERENCE which is a fixed multiple of RSENSE. A set resistor is provided having a resistance RSET.
Abstract: A DC-DC voltage converter is provided that includes a plurality of power channels and a controller. Each power channel is configured to provide a voltage output to an output node of the converter. Each power channel also includes a first sensing circuit configured to provide a primary feedback signal indicative of an output current of the power channel. Each power channel further includes an auxiliary sensing circuit to provided one or more auxiliary feedback signals indicative of an output current of each of the respective other power channels. The controller is configured to control each of the power channels based at least in part on the primary feedback signal and the one or more auxiliary feedback signals.
Abstract: A DC to DC converter circuit includes circuitry for generating a PWM waveform signal at a phase node of a DC to DC converter responsive to an input voltage and a monitor output voltage. The circuitry further includes a high side switching transistor connected between the input voltage and a phase node and a low side switching transistor connected between the phase node and ground. An output filter is connected to the circuitry for generating the PWM waveform signal. The output filter includes an inductor having a first side connected to the phase node and a second side connected to an output voltage node. Detection circuitry detects zero current crossings in the inductor responsive to a voltage across the high side switching transistor and a voltage across the low side switching transistor.
Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
Abstract: An apparatus for monitoring current for a motor drive including at least high-side and low-side switching transistors includes a driver circuit for driving a gate of the low-side switching transistor. First circuitry measures a drain to source voltage across the low-side switching transistor and generates a voltage output responsive thereto. Second circuitry has a first state of operation that samples the voltage output of the first circuitry when the low-side switching transistor is turned on and has a second state of operation to sample the voltage output of the first circuitry when the low-side switching transistor is turned off. The second circuitry further generates a monitored output current responsive to the sampled voltage output.
Abstract: A method for charging a battery of an electronic device using a connected a/c power adapter comprising the steps of determining a state of a transistor connecting a regulated voltage to the battery and switching a charging current applied to the battery between a quick charge level and a trickle charge level responsive to the state of the transistor.
Type:
Application
Filed:
April 15, 2009
Publication date:
August 6, 2009
Applicant:
INTERSIL AMERICAS INC.
Inventors:
Eric Magne Solie, Ronil Dipak Patel, Tu A. Bui
Abstract: A dimming control circuit for dimming light emitting diodes receives an AC input voltage signal from a dimming circuit. The control circuit includes a power stage and a current control loop coupled to the power stage. An AC detector is operable to detect an instantaneous value of the AC input voltage signal and to generate a signal indicating whether the AC input voltage signal is present or absent. A current control circuit is operable responsive to the signal to adjust the operation of the current control loop and to control current through the light emitting diodes to achieve the desired dimming, and to prevent inrush current on the AC input voltage signal.
Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).
Type:
Grant
Filed:
November 30, 2005
Date of Patent:
July 28, 2009
Assignees:
Intersil Americas Inc., University of Central Florida
Inventors:
Javier A. Salcedo, Juin J. Liou, Joseph C. Bernier, Donald K. Whitney
Abstract: A phase-modulated, double-ended, full-bridge topology-based DC-AC converter supplies AC power to a load, such as a cold cathode fluorescent lamp used to back-light a liquid crystal display. First and second converter stages generate respective first and second sinusoidal voltages having the same frequency and amplitude, but having a controlled phase difference therebetween. By employing a voltage controlled delay circuit to control the phase difference between the first and second sinusoidal voltages, the converter is able to vary the amplitude of the composite voltage differential produced across the opposite ends of the load.
Type:
Grant
Filed:
July 6, 2005
Date of Patent:
July 21, 2009
Assignee:
Intersil Americas Inc.
Inventors:
Robert L. Lyle, Jr., Steven P. Laur, Zaki Moussaoui
Abstract: Methods of forming and structures of a relatively large bipolar transistor is provided. The method includes forming a collector in a semiconductor region. Forming a base contiguous with a portion of the collector. Forming a plurality of emitters contiguous with portions of the base. Forming a common emitter interconnect and forming ballast emitter resistors for select emitters. Each ballast emitter resistor is coupled between an associated emitter and the common emitter interconnect. Each ballast resistor is further formed to have a selected resistance value. The selected resistance value of each ballast resistor is selected so the values of the ballast resistors vary in a two dimensional direction in relation to a working surface of the bipolar transistor.
Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.
Abstract: An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.
Type:
Application
Filed:
March 23, 2009
Publication date:
July 16, 2009
Applicant:
INTERSIL AMERICAS INC.
Inventors:
Dong ZHENG, Robert L. LYLE, JR., Barry HARVEY, Brian B. NORTH
Abstract: A phase-modulated, double-ended, half-bridge topology-based DC-AC converter supplies AC power to a load, such as a cold cathode fluorescent lamp used to back-light a liquid crystal display. First and second converter stages generate respective first and second sinusoidal voltages having the same frequency and amplitude, but having a controlled phase difference therebetween. By employing a voltage controlled delay circuit to control the phase difference between the first and second sinusoidal voltages, the converter is able to vary the amplitude of the composite voltage differential produced across the opposite ends of the load.
Type:
Grant
Filed:
July 6, 2005
Date of Patent:
July 14, 2009
Assignee:
Intersil Americas Inc.
Inventors:
Robert L. Lyle, Jr., Steven P. Laur, Zaki Moussaoui
Abstract: A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.
Type:
Application
Filed:
February 3, 2009
Publication date:
July 9, 2009
Applicant:
INTERSIL AMERICAS INC.
Inventors:
Dong Zheng, Phillip J. Benzel, Joy Jones, Alexander Kalnitsky, Perumal Ratnam
Abstract: Provided herein are input stages, and operation amplifiers including input stages. In an embodiment, an input stage includes a complimentary differential input transconductor, first and second npn-pnp current mirrors, and first and second pnp-npn current mirrors. The complimentary differential input transconductor includes a pair of differential inputs that accept a pair of voltage signals, a first pair of complimentary differential outputs that output current signals I1 and I2, and a second pair of complimentary differential outputs that output current signals I3 and I4. Each current mirror accepts one of the current signals I1, I2, I3 and I4, and outputs a pair of current signals (e.g., I1? and I1?) that are proportional to the accepted current signal (e.g., I1). Current signals I1? and I3? are added to produce a first output current (Iout) of the input stage. Current signals I2? and I4? are added to produce a second output current (Iout_bar) of the input stage.
Abstract: Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin.
Type:
Application
Filed:
March 11, 2009
Publication date:
July 2, 2009
Applicant:
INTERSIL AMERICAS INC.
Inventors:
Steven Patrick Laur, Wei Dong, Mehul Dilip Shah
Abstract: A current-sensing and correction circuit having programmable temperature compensation circuitry that is incorporated into a pulse width modulation controller of a buck mode DC—DC converter. The front end of the controller contains a sense amplifier, having an input coupled via a current feedback resistor to a common output node of the converter. The impedance of a MOSFET, the current through which is sampled by a sample and hold circuit is controlled by the sense amplifier unit. A sensed current correction circuit is coupled between the sample and hold circuit and the controller, and is operative to supply to the controller a correction current having a deterministic temperature-compensating relationship to the sensed current. The ratio of correction current to sensed current equals to value of one at a predetermined temperature, and has other values at temperatures other than at that temperature.