Patents Assigned to Intersil
  • Patent number: 7750426
    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: July 6, 2010
    Assignee: Intersil Americas, Inc.
    Inventors: Dev Alok Girdhar, Michael David Church, Alexander Kalnitsky
  • Publication number: 20100149879
    Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.
    Type: Application
    Filed: February 24, 2010
    Publication date: June 17, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
  • Patent number: 7737727
    Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: June 15, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Anatoly Aranovsky
  • Publication number: 20100141225
    Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.
    Type: Application
    Filed: June 26, 2009
    Publication date: June 10, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Robert H. Isham, Weihong Qiu
  • Patent number: 7732941
    Abstract: A circuit provides multi-module current sharing for circuit modules. The circuit includes an error amplifier having a negative and a positive input and an output. The positive input of the error amplifier is connected to a reference voltage. A buffered differential amplifier has an output connected to the negative input of the error amplifier and a positive and a negative input. A correction current is sourced to the negative input of the buffered differential amplifier. A resistor connected to the negative input of the buffered differential amplifier has a value that controls the amount of current correction applied to the negative input of the buffer differential amplifier by the current correction source.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: June 8, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Chun Cheung, Stan Wietecha
  • Patent number: 7728649
    Abstract: An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 1, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Robert W. Webb, Gregg D. Croft
  • Patent number: 7729427
    Abstract: A system and method for transferring data between a transmitter and a receiver over a single conductor is disclosed. During a data transfer operation of bit of information, the voltage level on the conductor is changed from a first voltage level to a second voltage level and maintained at the second voltage level for a predetermined duration of time. The predetermined duration of time is determined by the logical state of the data bit being transmitted. Upon expiration of the predetermined duration of time the voltage level on the conductor is driven back to substantially the first voltage level.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: June 1, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Chung Y. Kwok
  • Publication number: 20100127684
    Abstract: A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between second and fourth nodes and the amplifier control circuit is coupled between first and third nodes. The current generator develops a first current through the amplifier control circuit and a second current through the bias circuit. The sense circuit has a current path coupled to the first node and is controlled by the third node to develop a sense voltage indicative of current through the main switch.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 27, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Stepan Iliasevitch
  • Publication number: 20100127680
    Abstract: A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 27, 2010
    Applicant: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Lawrence Pearce
  • Publication number: 20100129975
    Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.
    Type: Application
    Filed: February 1, 2010
    Publication date: May 27, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventor: James D. Beasom
  • Publication number: 20100127679
    Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 27, 2010
    Applicant: Intersil Americas Inc.
    Inventor: Harold William Satterfield
  • Patent number: 7724080
    Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: May 25, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Gwilym Francis Luff
  • Patent number: 7724069
    Abstract: A switch circuit, which selectively couples first and second switch nodes together and which enables the first and second switch nodes to operate in an extended voltage range, includes a secondary voltage rail, a switch device, a body driver, a rail control switch, and a switch control circuit. The rail control switch clamps the secondary voltage rail to a primary voltage rail during normal voltage range operation, but otherwise releases the secondary voltage rail to float. The body driver clamps the body of the switch to the secondary voltage rail when turned on, and when turned off, forward biases to allow voltage of said secondary voltage rail to follow voltage of the switch nodes into the extended voltage range through the switch. The switch control circuit includes a latch circuit which ensures that the switch remains either turned on or turned off during extended voltage operation.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 25, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Robert W. Webb
  • Publication number: 20100117883
    Abstract: A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 13, 2010
    Applicant: Intersil Americas Inc.
    Inventors: T.C.L. Gerhard Sollner, Michael P. Anthony
  • Publication number: 20100117198
    Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.
    Type: Application
    Filed: January 19, 2010
    Publication date: May 13, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
  • Patent number: 7714415
    Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 11, 2010
    Assignee: Intersil Americas, Inc.
    Inventors: Young-Gon Kim, Nikhil Vishwanath Kelkar, Louis Elliott Pflughaupt
  • Patent number: 7714851
    Abstract: Video line drivers that operate using a single external supply voltage, without the need for large external capacitors (e.g., 470 uF) on the output, are provided. In accordance with an embodiment, a video line driver includes a charge pump and a plurality of amplifiers. The charge pump uses the single external supply voltage to produce a further voltage having an opposite polarity than the external supply voltage. The plurality of amplifiers are each powered by the external supply voltage and the further voltage produced by the charge pump. Each amplifier receives a portion of a video signal and outputs an amplified version of the received portion of the video signal. The video signal can include, e.g., an R portion, a G portion and a B portion, or a Y portion, a Pb portion and a Pr portion. This abstract is not intended to be a complete description of the invention.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: May 11, 2010
    Assignee: Intersil Americas Inc.
    Inventor: Sameer Vuyyuru
  • Publication number: 20100109631
    Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.
    Type: Application
    Filed: January 14, 2010
    Publication date: May 6, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventor: James E. Vinson
  • Publication number: 20100110299
    Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.
    Type: Application
    Filed: March 26, 2009
    Publication date: May 6, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: David W. Ritter, Robert David Zucker, Warren Craddock
  • Publication number: 20100110288
    Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. The compensating is selectively locked and reset in response to specific conditions being detected, e.g., a locking condition and a reset condition.
    Type: Application
    Filed: October 20, 2009
    Publication date: May 6, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: David W. Ritter, Warren Craddock, Robert David Zucker