Abstract: A control circuit for generating a control signal to add phases to a multiphase voltage regulator. The control circuit includes an input for receiving an error correction voltage from an error amplifier of the multiphase voltage regulator and at least one output for providing a PWM control signal. Control circuitry generates at least one PWM control signal to add a phase to the multiphase voltage regulator responsive to a determination that the error correction voltage has exceeded a threshold level.

Abstract: A load compensation circuit for a switching regulator including a comparator circuit and an adjustable voltage source. The switching regulator includes a switch circuit for converting an input voltage to a regulated output voltage and for driving a load current, and a controlled switch driver circuit having a supply voltage input and an output driving the switch circuit. The comparator circuit senses the load current and adjusts a voltage control signal to adjust switching efficiency based on the load current. The voltage source has an input receiving the voltage control signal and an output for providing a switch supply voltage to the supply voltage input of the switch driver circuit, where the voltage source adjusts the switch supply voltage based on the voltage control signal. A method of compensating a switching regulator based on load including sensing load current and adjusting the switch supply voltage to adjust switching efficiency.

Abstract: A Buck switching regulator includes first Buck switching regulator circuitry is operable to generate a first output voltage from an input voltage and operable to generate a first sensed voltage having a value that is proportional to an output current being provided by the first Buck switching regulator circuitry. The first Buck switching regulator circuitry receives an input current and operates at a first duty cycle determined by a duty cycle signal. Input current sensing circuitry includes second Buck switching regulator circuitry coupled to the first Buck regulator switching circuitry to receive the duty cycle signal and to receive the first sensed voltage as an input voltage to the second Buck switching regulator circuitry. The second Buck switching regulator circuitry is operable responsive to the duty cycle signal to generate a second output voltage from the first sensed voltage.

Abstract: A charging circuit included on a single integrated circuit including first circuitry for generating a charging current responsive to an input voltage source. The input voltage source may comprise a USB voltage source or a non-USB voltage source. A USB detection circuit determines whether the input voltage source comprises the USB voltage source or the non-USB voltage source.

Abstract: Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.

Abstract: An antenna module with a detector and an associated canceller is disclosed. The detector may also detect interference and spurs. In one embodiment, an antenna module can include: an antenna configured to receive an electromagnetic signal in a signal path; an amplifier configured to amplify the received electromagnetic signal, and to provide the amplified signal at a first node; a filter configured to receive the amplified signal from the first node, and to provide a filtered signal output therefrom; and a noise canceller and a detector integrated in the signal path at the first node.

Abstract: An embodiment of a power-supply controller is operable to couple a first node of a first inductor to first and second reference nodes, the first inductor composing a first phase of a power supply and having a second node coupled to an output node of the power supply. The controller is also operable to couple a first node of a second inductor to third and fourth reference nodes, the second inductor composing a second phase of the power supply and having a second node. Furthermore, the controller is operable to uncouple the second node of the second inductor from the output node of the power supply. For example, where the first and second inductors are magnetically coupled, such a controller allows the power supply to operate as an uncoupled-inductor (UI) power supply in one mode, and as a coupled-inductor (CI) power supply in another mode.

Abstract: A buck boost voltage converter circuit, comprises a capacitor pump circuit for boosting an input voltage in a first mode of operation when an input voltage is below a desired voltage level. A buck converter circuit provides the output voltage responsive to the boosted input voltage from the capacitor pump circuit in the first mode of operation and provides the output voltage responsive to the input voltage in a second mode of operation when the input voltage is above the desired voltage level.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A dynamically configurable multiple wavelength adapted photodetector (PD) integrated circuit includes a PD array having a center bank of electrically isolated PD sections, and a first and a second side channel bank of electrically isolated PD sections on opposing sides of the center PD bank for receiving light and outputting electrical signals. A dynamically configurable switching matrix having a first plurality of inputs is coupled to outputs of the PD sections and a second plurality of inputs is provided for receiving control signals which select from a plurality of different switch configurations. The switch configurations set which of the PD sections are coupled to particular ones of a plurality of matrix outputs provided by the switching matrix. A structure providing switching matrix configuration information is coupled to the second plurality of inputs of the switching matrix to selects specific ones from the plurality of different switch configurations.

Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process including, applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and forming interconnect metal layers.

Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.

Abstract: A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

Abstract: An integrated circuit controller for controlling the operation of a voltage converter which includes a first comparator for comparing a voltage associated with an input of a boost converter with a threshold voltage and generating a control signal in response thereto. A second comparator compares a second voltage associated with an output of the boost converter with the threshold voltage and generates a second control signal in response thereto. Driver circuitry generates a first switching transistor drive signal and a second switching transistor drive signal. The first switching transistor drive signal is used for driving an upper gate switching transistor of a buck converter. The second switching transistor drive signal may be configured in a first mode of operation to drive a lower gate switching transistor of the buck converter and may be configured in a second mode of operation to drive a switching transistor of the boost converter.

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract: A buck regulator comprises an upper switching transistor connected between a voltage input node and a phase node. A lower switching transistor is connected between the phase node and a ground node. An inductor is connected between the phase node and an output voltage node. Circuitry generates control signals to the upper switching transistor and the lower switching transistor responsive to the output voltage and a reference voltage. The control signals to the lower switching transistor selectively turn off the lower switching transistor responsive to a current direction through the lower switching transistor and an indication of whether a voltage error signal has been clamped at a selected level.

Abstract: An LED driver controller comprises a voltage regulator for controlling an output voltage to a top of a plurality of LED strings responsive to at least a reference voltage. A plurality of first circuitries each associated with a node at a bottom of each of the plurality of LED strings compares a voltage at the bottom of each of the plurality of LED strings with a high reference voltage and a low reference voltage. Control logic generates a first control signal when the voltage at the bottom of each node of the plurality of LED strings exceeds the high reference voltage and generates a second control signal when the voltage at least one of node of the plurality of LED strings falls below the low reference voltage. Second circuitry responsive to the first control signal and the second control signal generates the reference voltage.

Abstract: A circuit for generating an output voltage to a top node of a plurality of LED strings. The circuit includes an inductor having a load current flowing therethrough and a switching transistor responsive to a switching control signal. An integrator generates a compensation voltage responsive to a voltage at a bottom node of the LED string and a reference voltage. Circuitry for combining an offset with the compensation voltage is responsive to the compensation voltage and the load current through the inductor. The offset is generated only during a step load change of the load current and substantially reduces voltage transients from the compensation voltage and the output voltage. A summation circuit sums the compensation voltage including the offset with at least the voltage at the bottom node of the LED string to generate a first control signal. A latch generates the switching control signal responsive to the first control signal and a leading edge blanking signal.

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Abstract: A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.