Patents Assigned to Intersil
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Patent number: 6911790Abstract: A multiplexed high voltage DC-AC driver including multiple DC-AC switches and decoder logic. Each DC-AC switch receives an input DC voltage and is operative, when enable, to toggle its output at a rate based on a master clock signal and at a voltage based on the input DC voltage. The DC-AC switches include one or more high side switches and a low side switch. The low side switch includes a clock inverter and operates out-of-phase relative to each high side switch. The decoder logic enables selected ones of the high side switches and enables the low side switch when any high side switch is enabled.Type: GrantFiled: November 14, 2003Date of Patent: June 28, 2005Assignee: Intersil Americas Inc.Inventor: Grady M. Wood
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Patent number: 6909146Abstract: A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities.Type: GrantFiled: May 21, 1999Date of Patent: June 21, 2005Assignee: Intersil CorporationInventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller
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Publication number: 20050128005Abstract: A transconductance amplifier with multi-emitter structure for balancing current of a multi-phase regulator including multiple transistors, a bias current device, multiple current mirrors, and multiple current sources. Each transistor has first and second current terminals and a current control terminal receiving a corresponding one of multiple sense voltages. Each sense voltage is indicative of output inductor current of a corresponding phase of the multi-phase regulator. The bias current device is coupled to the first current terminal of each transistor. Each current mirror has an input coupled to a second current terminal of a corresponding transistor and an output coupled to a corresponding one of multiple correction nodes. Each current source is coupled to a corresponding one of multiple correction nodes. In this manner, each correction node provides a correction current for a corresponding phase of the regulator.Type: ApplicationFiled: March 17, 2004Publication date: June 16, 2005Applicant: Intersil Americas Inc.Inventors: Xuening Li, Thomas Jochum
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Publication number: 20050128776Abstract: A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.Type: ApplicationFiled: March 10, 2004Publication date: June 16, 2005Applicant: Intersil Americas Inc.Inventors: Noel Dequina, Donald Preslar, Paul Sferrazza
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Publication number: 20050131557Abstract: A linear predictive system for a DC-DC converter including a linear predictive controller, first and second adders and a multiplier. The DC-DC converter generates an output signal and includes a digital compensation block that converts a feedback error signal into a main duty cycle signal. The linear predictive controller predicts linear changes of the main duty cycle signal in response to changes of the output signal and provides a predictive duty cycle signal. The first adder subtracts the predictive duty cycle signal from the main duty cycle signal to provide a duty cycle delta. The multiplier multiplies the duty cycle delta by a gain factor to provide a duty cycle delta sample. The second adder adds the duty cycle delta sample to the first duty cycle signal to generate an adjusted duty cycle signal.Type: ApplicationFiled: April 19, 2004Publication date: June 16, 2005Applicant: Intersil Americas Inc.Inventor: Zaki Moussaoui
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Patent number: 6906536Abstract: An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.Type: GrantFiled: November 24, 2003Date of Patent: June 14, 2005Assignee: Intersil Americans Inc.Inventors: Lawrence George Pearce, William David Bartlett
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Patent number: 6903914Abstract: A DC-DC converter has an output bus coupled to power a load. A voltage transient compensation circuit has a first switch between a voltage input bus and the output bus, and a second switch between the output bus and a flyback transformer coupled to a reference voltage terminal. When the voltage on the output bus drops below a first threshold, the first switch couples and thereby transfers energy from the voltage input bus to the voltage output bus and the load. When the voltage on the output bus exceeds a second threshold, the second switch is closed, transferring energy from the output bus to an input winding of the flyback transformer. When the voltage on the output bus drops back in a range between the two thresholds, the second switch is opened, and the flyback transformer transfers stored energy back to the voltage input bus.Type: GrantFiled: December 2, 2003Date of Patent: June 7, 2005Assignee: Intersil Americas, Inc.Inventor: Zaki Moussaoui
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Patent number: 6902967Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.Type: GrantFiled: March 26, 2004Date of Patent: June 7, 2005Assignee: Intersil Americas Inc.Inventor: James D. Beasom
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Publication number: 20050117268Abstract: A DC-DC converter has an output bus coupled to power a load. A voltage transient compensation circuit has a first switch between a voltage input bus and the output bus, and a second switch between the output bus and a flyback transformer coupled to a reference voltage terminal. When the voltage on the output bus drops below a first threshold, the first switch couples and thereby transfers energy from the voltage input bus to the voltage output bus and the load. When the voltage on the output bus exceeds a second threshold, the second switch is closed, transferring energy from the output bus to an input winding of the flyback transformer. When the voltage on the output bus drops back in a range between the two thresholds, the second switch is opened, and the flyback transformer transfers stored energy back to the voltage input bus.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Applicant: Intersil Americas Inc.Inventor: Zaki Moussaoui
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Publication number: 20050110472Abstract: A PWM system that minimizes output ripple of a multiphase DC-DC converter which converts N input voltages including at least one dissimilar input voltage. The PWM system includes PWM waveform logic that generates N PWM signals including a PWM signal for each of the N input voltages, and PWM control logic that optimizes relative phases of the N PWM signals based on voltage levels of the N input voltages. Various circuits and/or methods are contemplated for optimizing phase, including, for example, centering pulses for each PWM cycle, distributing pulses based on predetermined optimal phase angles, determining input voltage levels and selecting predetermined optimal phase angles, generating phase signals employing predetermined phase angles, measuring input voltages and calculating optimal phase angles, and using PLL logic or the like to measure and equalize off-times between PWM pulses.Type: ApplicationFiled: February 26, 2004Publication date: May 26, 2005Applicant: Intersil Americas Inc.Inventors: Matthew Harris, James Leith, Brandon Day
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Publication number: 20050110561Abstract: An IC including a margining control amplifier circuit, first and second offset pins, a margining control pin, select logic, and a mirror amplifier circuit. The margining control amplifier circuit drives current at an output to control voltage at an input based on a reference voltage. The first and second offset pins are provided to couple an external margining voltage divider. The margining control pin has at least two states including an up state and a down state. The select logic selectively switches the output of the margining control amplifier circuit between the first and second offset pins and selectively switches the input of the margining control amplifier circuit between the second and first offset pins based on a state of the margining control pin. The mirror amplifier circuit mirrors voltage across the first and second offset pins across a first margining resistor.Type: ApplicationFiled: March 30, 2004Publication date: May 26, 2005Applicant: Intersil Americas Inc.Inventors: Gustavo Mehas, James Leith, Brandon Day
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Patent number: 6897636Abstract: A multi-phase DC—DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.Type: GrantFiled: February 4, 2003Date of Patent: May 24, 2005Assignee: Intersil Americas Inc.Inventor: Matthew B. Harris
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Patent number: 6897103Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.Type: GrantFiled: February 12, 2003Date of Patent: May 24, 2005Assignee: Intersil Americas Inc.Inventor: James D. Beasom
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Patent number: 6898123Abstract: A method and circuit for setting a reference voltage in a dual floating gate circuit is disclosed. During a set mode, a first and second floating gate are programmed to different charge levels that are a function of an input set voltage capacitively coupled to the first floating gate during the set mode. During a read mode, this difference in charge level is used by the dual floating gate circuit to generate a reference voltage that is a function of the input set voltage, and is preferably equal to the input set voltage.Type: GrantFiled: January 7, 2003Date of Patent: May 24, 2005Assignee: Intersil Americas Inc.Inventor: William H. Owen
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Publication number: 20050104540Abstract: A multiplexed high voltage DC-AC driver including multiple DC-AC switches and decoder logic. Each DC-AC switch receives an input DC voltage and is operative, when enabled, to toggle its output at a rate based on a master clock signal and at a voltage based on the input DC voltage. The DC-AC switches include one or more high side switches and a low side switch. The low side switch includes a clock inverter and operates out-of-phase relative to each high side switch. The decoder logic enables selected ones of the high side switches and enables the low side switch when any high side switch is enabled.Type: ApplicationFiled: November 14, 2003Publication date: May 19, 2005Applicant: Intersil Americas Inc.Inventor: Grady Wood
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Publication number: 20050105307Abstract: A tracking soft start circuit architecture contains a plurality of soft start circuits for generating a plurality of soft start voltages during startup for application to associated power supply terminals of a power supply system. The soft start circuits are interconnected in such a manner that prevents any soft start circuit from generating a soft start voltage waveform until all of the controlled power output devices have been brought to the same prescribed state of operation, that is, all power FET gates are precharged and their source voltages match each other.Type: ApplicationFiled: January 14, 2004Publication date: May 19, 2005Applicant: Intersil Americas Inc. State of Incorporation: DelawareInventors: William Shearon, Raymond Giordano, Sumer Can
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Patent number: 6894928Abstract: An apparatus and method is provided for adjusting a reference voltage at an output terminal of a floating gate reference voltage generator circuit in order to improve the accuracy of the reference voltage at an input terminal of a load circuit. The apparatus and method compensates for the voltage drop produced between the output terminal of the reference voltage generator circuit and the input terminal of the load circuit, and includes a capacitor for capacitively coupling the voltage at the input terminal of said load circuit to a floating gate, and a differential amplifier operatively coupled to the floating gate which acts in response to the capacitively coupled load circuit input voltage to adjust the voltage at the output terminal such that the voltage at the input terminal of the load circuit becomes equal to the reference voltage.Type: GrantFiled: January 28, 2003Date of Patent: May 17, 2005Assignee: Intersil Americas Inc.Inventor: William H. Owen
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Patent number: 6894349Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.Type: GrantFiled: March 22, 2002Date of Patent: May 17, 2005Assignee: Intersil Americas Inc.Inventor: James D. Beasom
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Publication number: 20050093525Abstract: A multiphase DC-DC converter architecture, in which respectively different channels have different operational performance parameters. These different parameters are selected so as to enable the converter to achieve an extended range of high efficiency. The converter contains a combination of one or more fast response time-based converter channels, and one or more highly efficient converter channels in respectively different phases thereof and combines the outputs of all the channels. The efficiency of the asymmetric multiphase converter is higher at light loads (up to approximately 12 amps), enabling it to offer longer battery life in applications that spend most of their operating time in the leakage mode, as noted above.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Applicant: Intersil Americas Inc.Inventors: Michael Walters, Shea Petricek
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Publication number: 20050088212Abstract: A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.Type: ApplicationFiled: February 10, 2004Publication date: April 28, 2005Applicant: Intersil Americas Inc.Inventors: James Leith, Gustavo Mehas