Abstract: A D/A converter including first and second R-R2 resistor ladders and a set of SPDT switches. The first R-2R resistor ladder includes N type resistors coupled between a common voltage node and an output voltage node and the second R-2R resistor ladder includes P type resistors coupled between the common and output voltage nodes. The R-2R resistor ladders have multiple common switch terminals, each coupling an N type 2R resistor to a corresponding P type 2R resistor. Each SPDT switch is responsive to a data bit for switching a common switch terminal between the common voltage and a reference voltage. Each N type resistor may be formed in a PWell coupled to the common (or more negative) voltage and each P type resistor may be formed in an NWell coupled to the reference (or more positive) voltage. The SPDT switches may be configured with equivalent switch path impedances.

Abstract: An IC including a margining control amplifier circuit, first and second offset pins, a margining control pin, select logic, and a mirror amplifier circuit. The margining control amplifier circuit drives current at an output to control voltage at an input based on a reference voltage. The first and second offset pins are provided to couple an external margining voltage divider. The margining control pin has at least two states including an up state and a down state. The select logic selectively switches the output of the margining control amplifier circuit between the first and second offset pins and selectively switches the input of the margining control amplifier circuit between the second and first offset pins based on a state of the margining control pin. The mirror amplifier circuit mirrors voltage across the first and second offset pins across a first margining resistor.

Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract: A wireless receiver including a receive chain, a synchronization processor, a memory, a combiner and a soft decision processor. The synchronization processor determines a frequency response of the wireless channel using synchronization data transmitted in the wireless channel. The memory stores a compensation vector indicative of a frequency response of receive chain filtering. The combiner combines the compensation vector with the wireless channel frequency response to provide a compensated frequency response. The soft decision processor uses the compensated frequency response to evaluate data decisions. The compensation vector is based on measurement or estimation of the frequency response of the receive chain. The combiner may be based on multiplication or addition. The wireless receiver may include an FEQ. The synchronization processor generates FEQ coefficients for programming the FEQ taps.

Abstract: A high voltage differential amplifier including an input differential pair of low voltage transistors, a sense differential pair of low voltage transistors, first and second high voltage transistors, a low voltage bias transistor, a cascaded pair of low voltage transistors, and an output pair of high voltage transistors. The sense differential pair has a pair of control terminals that detect a common mode voltage of the differential input signal, and establishes a sense node which follows the common mode voltage. The first high voltage device is coupled to the sense node to establish bias node voltage levels which track the common mode voltage, including an output bias node biasing the output pair and a cascade bias node biasing the cascaded pair. In this manner, the terminals of the low voltage devices slide up or down with the common mode voltage and are protected from high voltage levels.

Abstract: In order to minimize switching-induced electromagnetic interference in a power supply switching circuit of the type used to control the AC power for multiple high voltage devices, such as cold cathode fluorescent lamps employed for backlighting a large scale liquid crystal display, the gating signals that are used to switch lamp-driving inverter circuits ON and OFF are staggered, or slightly offset in time, so that no two switching devices will be switched at the same time. By slightly offset in time is meant that the time differential between any pair of switching signals is relatively small compared to the period of the switching signal frequency. This has the effect of spreading out and thereby diminishing the magnitude of the spectral content of both capacitively and inductively coupled transients that are produced at switching times of the inverter circuits.

Abstract: A distributed controller and DC voltage switch-driver system supplies AC power to a cold cathode fluorescent lamp of the type used to backlight a liquid crystal display. The system includes a local controller and lamp operation-monitoring subsystem, which generates two pairs of low voltage drive signals. These drive signals are distributed over low voltage wires to respective pairs of step-up transformer-driving switches installed at opposite ends of the lamp. The high voltage AC outputs of the two transformers have the same frequency, but opposite phase, to reduce the voltage ratings of the components that are installed at the opposite ends of the lamp. The use of low voltage connections from the local controller to driver circuitry at the far end of the lamp serves to reduce the cost of the components, and results in lower emitted noise and lower energy lost to capacitive coupling.

Abstract: An AC power supply system modulates a high frequency switching signal with a pulse width modulation (PWM) signal to produce a composite signal. The duty cycle of the PWM component of the composite signal is used to control the brightness of a cold cathode fluorescent lamp for backlighting a liquid crystal display.

Abstract: The problem of charge leakage in the AC compensation filter for the error amplifier of a pulse width modulation (PWM)-based DC—DC converter is effectively obviated by controllably sampling and storing the voltage across the AC compensation filter, in response to a transition of the operation of a DC power supply from run or active mode to quiescent or sleep mode. The sampled voltage is retained as a compensation voltage throughout the quiescent mode, so that it will be immediately available to the PWM circuitry at the termination of the quiescent interval. This serves to ensure a relatively smooth (low noise) power supply switch-over during a subsequent transition from quiescent to active mode.

Abstract: A voltage reference filter for a subscriber line interface circuit removes unwanted noise on a DC reference voltage sourced by a device, such as a codec, and employed by the subscriber line circuit as a differential mode voltage baseline. The DC reference voltage is coupled via a high pass filter to the sense amplifier. The filter blocks the DC component of the reference voltage and passes noise components to the sense amplifier. The reference port of an amplifier between the sense amplifier and a codec receives the same (noisy) reference voltage AC-coupled to the sense amplifier, and performs common mode rejection of noise components riding on the DC reference.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Abstract: In order to derive a precise measurement of temperature and current in a synchronous buck DC-DC converter a synchronous conduction cycle measurement of the value of reverse conduction voltage (VON), and an asynchronous conduction cycle measurement of the value of body diode conduction voltage (VDF) of the low side power MOSFET are performed. These two measured values are then used as dual inputs to a two-dimensional to two-dimensional transform function (e.g., look-up table) that is effective to map the measured voltage values into output values for current (I) and temperature (T).

Abstract: A droop amplifier circuit for a DC-DC regulator including an amplifier, at least one first resistive device, a second resistive device, a third resistive device, and a first capacitive device. Each first resistive device is coupled between an output inductor (phase node or current sense node) and the amplifier's non-inverting input. The first capacitive device is coupled between the regulator output and the amplifier's output. The second resistive device is coupled between the regulator output and the amplifier's inverting input. The third resistive device is coupled between the amplifier's inverting input and output. A second capacitive device may be coupled between the regulator output and the amplifier's non-inverting input. A fourth resistive device may be coupled in parallel with the second capacitive device. A relatively small, simple and low performing amplifier is sufficient. Circuit area and power are reduced, and low input offset voltage is more easily achieved.

Abstract: A method of enabling and disabling diode emulation for a DC/DC converter which generates an output voltage including detecting a diode emulation request signal indicative of enabling or disabling diode emulation and delaying enabling or disabling diode emulation until after the output voltage begins changing. Diode emulation is enabled while the output voltage is decreasing or has reached a predetermined level and an optional delay may be included. Diode emulation is disabled while the voltage is increasing. A diode emulation control circuit includes a first circuit that determines when the output voltage is changing and a second circuit that selectively enables or disables diode emulation in response to a diode emulation enable/disable signal after the output voltage begins to change.

Abstract: A multi-phase DC/DC converter having an output voltage and including a plurality of converter channels. Each converter channel includes a converter channel input and a converter channel output. Each converter channel is configured for generating a converter channel current and for adjusting said converter channel current in response to a control signal electrically connected to each converter channel input. A control circuit generates an error signal representative of a comparison of the converter output voltage to a reference voltage. The control circuit includes a plurality of control circuit channels, each of which correspond to a converter channel. Each control circuit channel generates a channel current signal representative of a corresponding converter channel current, and generates a differential channel current signal representative of a comparison of the channel current signal to an average current signal.

Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal.