Abstract: Systems and methods for reducing the harmonic content of an oscillator are provided. More specifically, waveforms with reduced harmonics are provided, as are waveform generators for producing such waveforms. Such waveform generators can be used in or with a laser driver. However, the present invention is not meant to be limited to use with laser drivers. Rather, embodiments of the present invention are useful anywhere where harmonics resulting from an oscillating waveform need to be reduced.

Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

Abstract: The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Abstract: A multi-stage, push-pull driven, resonant DC-AC converter ties the center-taps of primary windings of respective push-pull stages together, and drives each center-tap with a current source. Tying the center-taps of the primary windings of the respective DC-AC converters' transformers together forces the voltages at these locations to be the same, so as to achieve mutual resonant synchronization between the two stages. Connecting the center-taps to a current source provides the necessary power for each stage and allows for a variation in current between stages, as the center-tap voltages track one another. The tied-together center-tap voltage is monitored to obtain the zero voltage switching required for efficient operation of switching devices of each DC-AC converter stage.

Abstract: A linear predictive system for a DC—DC converter including a linear predictive controller, first and second adders and a multiplier. The DC—DC converter generates an output signal and includes a digital compensation block that converts a feedback error signal into a main duty cycle signal. The linear predictive controller predicts linear changes of the main duty cycle signal in response to changes of the output signal and provides a predictive duty cycle signal. The first adder subtracts the predictive duty cycle signal from the main duty cycle signal to provide a duty cycle delta. The multiplier multiplies the duty cycle delta by a gain factor to provide a duty cycle delta sample. The second adder adds the duty cycle delta sample to the first duty cycle signal to generate an adjusted duty cycle signal.

Abstract: A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.

Abstract: A method of starting a DC—DC converter into a precharged output voltage including generating a reference voltage having a linear relationship with the output voltage such that the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level, and enabling output switching of the DC—DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage. Generating a reference voltage may include applying a first current based on the input voltage through two resistors to develop the minimum and maximum voltage levels, applying the first current in one direction through a third resistor, and applying a second current based on the output voltage through the third resistor in the opposite direction.

Abstract: A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.

Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Abstract: A reduced pin count, dual channel driver interface is configured to interface a supervisory controller with a plurality of multi-phase output channel switching circuits of a multi-phase DC-DC regulator. Each dual channel driver is configured for placement relatively close to output channel sense points, so as to effectively reduce the distance that would otherwise have to be traversed by noise sensitive voltage signals. Sensed current representative signals are processed within the dual driver for current balance between a respective multi driver pair, and are combined to supply the controller with the average current signal of the dual channels. The controller uses this average current-information to adjust respective pulse width modulation signals that are supplied to the dual channel drivers.

Abstract: A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.

Abstract: A phase activation control system for a multiphase DC/DC converter including an amplifier circuit and enable logic. The converter includes a first phase circuit providing a first PWM signal and has a reduce input for reducing duty cycle of the first PWM signal. The converter further includes a second phase circuit providing a second PWM signal and having an enable input and an increase input for increasing duty cycle of the second PWM signal. The amplifier circuit has an enable input, a current sense input for sensing output current of the converter and an output providing an adjust signal. The adjust signal is provided to the reduce input of the first phase circuit and to the increase input of the second phase circuit. The enable logic receives a phase enable signal and enables the amplifier circuit and the second phase circuit.

Abstract: A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.

Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.

Abstract: Ground skimming output stages that are designed to drive wideband signals with the ability to provide a high quality output signal all the way to the low supply rail are provided. In accordance with an embodiment of the present invention, the output stage of the present invention includes a translinear current controller, an output transistor and a current mirror. While not limited thereto, embodiments of the present invention only require a single positive power supply, consistent with the recent trend toward integrated circuits that only require a single low voltage power supply.

Abstract: A phase adjuster (10) includes a delay-locked loop (14) and an interpolator (34). The delay-locked loop (14) includes a sufficient number of delay stages (24) to maintain a ?/2 radians phase shift across the one delay stage (24?) of a voltage-controlled delay line (20). The output signals (28 and 30) to this one stage (24?) are filtered, output from the delay-locked loop (14), and input to the interpolator (34). Within the interpolator (34), these output signals (28 and 30) are weighted and combined. The ratio of the weighting applied to the output signals determines the resulting adjusted phase of an output clock signal (36). The weighting can be a time-varying signal or otherwise programmed as needed to achieve a desired phase shift that is independent of clock speed and process variation.

Abstract: A high voltage floating current sense amplifier circuit, including first and second resistive devices and a floating amplifier circuit, that senses current through a current sense device coupled between an output node and a battery node each referenced to a common node. The battery node couples to a positive terminal of a removable battery. The floating amplifier circuit drives a proportional current through the first resistor in order to maintain voltage across the first resistive device at approximately the same voltage as that across the current sense device. The second resistive device has a first end coupled to the common node and a second end coupled to receive the proportional current for developing a sense voltage indicative of current through the current sense device.

Abstract: A transconductance amplifier with multi-emitter structure for balancing current of a multi-phase regulator including multiple transistors, a bias current device, multiple current mirrors, and multiple current sources. Each transistor has first and second current terminals and a current control terminal receiving a corresponding one of multiple sense voltages. Each sense voltage is indicative of output inductor current of a corresponding phase of the multi-phase regulator. The bias current device is coupled to the first current terminal of each transistor. Each current mirror has an input coupled to a second current terminal of a corresponding transistor and an output coupled to a corresponding one of multiple correction nodes. Each current source is coupled to a corresponding one of multiple correction nodes. In this manner, each correction node provides a correction current for a corresponding phase of the regulator.

Abstract: Video line drivers that operate using a single external supply voltage, without the need for large external capacitors (e.g., 470 uF) on the output, are provided. In accordance with an embodiment, a video line driver includes a charge pump and a plurality of amplifiers. The charge pump uses the single external supply voltage to produce a further voltage having an opposite polarity than the external supply voltage. The plurality of amplifiers are each powered by the external supply voltage and the further voltage produced by the charge pump. Each amplifier receives a portion of a video signal and outputs an amplified version of the received portion of the video signal. The video signal can include, e.g., an R portion, a G portion and a B portion, or a Y portion, a Pb portion and a Pr portion. This abstract is not intended to be a complete description of the invention.

Abstract: The current limiting circuit of the present invention includes a transconductance amplifier having two outputs and forming a conventional feedback loop. A first output connects to an output transistor and a second output is a replica output used to form a rapid response feedforward path to control the gate of the output transistor, for example, an external MOSFET.