Abstract: A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices.

Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Abstract: A display device includes a display panel; and a backlight panel provided below the display panel and defining a plurality of regions. A first array of light emitting diodes (LEDs) is provided along a first direction, each LED of the first array being coupled to a first line. A driver is coupled to the first line to drive the LEDs coupled to the first line. A second array of LEDs is provided along a second direction, each LEDs of the second array being coupled to a second line. A lighting condition of the regions defined by the backlight panel is controlled by turning on or off the LEDs.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-coupled distributed diode. The bipolar transistor involves many N-type collector regions. Each N-type collector region has a central hole so that P-type material from an underlying P-type region extends up into the hole. A collector metal electrode covers the central hole forming a diode contact at the top of the hole. When the distributed diode conducts, current flows from the collector electrode, down through the many central holes in the many collector regions, through corresponding PN junctions, and to an emitter electrode disposed on the bottom side of the IC. The RBJT and distributed diode integrated circuit has emitter-to-collector and emitter-to-base reverse breakdown voltages exceeding twenty volts. The collector metal electrode is structured to contact the collector regions, and to bridge over the base electrode, resulting in a low collector-to-emitter voltage when the RBJT is on.

Abstract: A flyback converter involves a bipolar transistor (BJT) and a parallel-connected diode as the rectifying element in the secondary side of the converter. The transformer of the converter has a primary winding, a first secondary winding, and a second secondary winding. A first end of the first secondary winding is coupled to the BJT base. A first end of the second secondary winding is coupled to the BJT collector and to the anode of the diode. The first and second secondary windings are wound such that when primary winding current stops, pulses of current flow out of the first ends of the first and second secondary windings. These currents are such that the BJT is maintained in saturation throughout at least most of the time current flows through the rectifying element, thereby achieving a low forward voltage across the rectifying element, reducing conduction loss, and increasing converter efficiency.

Abstract: A system for communicating with a host using control signals over a 1-wire interface is disclosed. The system includes a driver coupled to the host by the 1-wire interface. Control signals are transmitted from the host to the driver for decoding by the driver controller. The control signals are pulse width modulation format signals which are interpreted by the driver as binary encoded command mode signals or analog encoded command mode signals, depending upon when the signals are received in relation to a preamble pulse and a post-amble pulse.

Abstract: An arrangement of a mother circuit board and daughter circuit boards in a power instrument improves current and voltage capabilities. A mother board is mounted to a base panel of an enclosure, and a number of daughter boards are attached to and extend from the mother board. Each daughter board has substantially identical circuitry and produces substantially the same amount of current. The daughter boards together provide a total output current equal to a sum of each individually generated current. The amount of power generated by the instrument can be increased by attaching additional daughter boards to the mother board. The total current produced by the daughter boards is provided to and output from the mother board via a low inductance output path. The low inductance output path ensures that a sudden increase in current does not result in a large voltage spike that adversely affects instrument operation.

Abstract: A usage pattern identifies time periods when an electrical apparatus is likely to be powered-up or not in use. Power provided to an electrical apparatus is increased during time periods that the electrical apparatus is likely to be powered-up. Similarly, the power provided to the electrical apparatus is reduced or removed during time periods that the electrical apparatus is likely to be out of use or idle. The usage pattern is continually updated and refined by collecting usage data during user interaction with the electrical apparatus.

Abstract: A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N? layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode.

Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.

Abstract: A 1-wire communication protocol and interface circuitry for communication between a host controller and a LED driver is provided. The 1-wire communication protocol is configured such that both PWM signals and DC current setting commands for programming the LED driver may be transmitted from the host controller to the LED driver via the same 1-wire interface. The 1-wire communication protocol uses the length of the pulses (pulse width), rather than the number of pulses, to distinguish between different modes of communication (PWM signal transmission mode or command pulse transmission mode) and different commands of the same type (specific DC current programming commands, or specific average PWM drive current for the LED, within each transmission mode). Because the same 1-wire interface is used for transmitting both PWM signals and DC current commands, integrated circuits for the host controller and the LED driver do not require an additional wire or pin.

Abstract: LED junction temperature is determined in real time using the LED itself as the temperature sensor for directly measuring the LED junction temperature. In addition, temperature measurements from a silicon diode placed in proximity to the LED are also used to complement the temperature measurements from the LED itself. Arbitration is performed among temperature measurements from the LED and temperature measurements from the silicon diode to determine a temperature of the LED junction. The determined LED junction temperature may be used to make adjustments to the LED drive current. Temperature measurements from the LED are made in real time during actual operation by applying snooping currents to the LED during off-times of the PWM cycles of the LED, without interrupting normal operation of the LED.

Abstract: A solar cell device includes a solar cell section configured to output a first voltage upon receiving light. A charge pump circuit includes a first charge pump. The first charge pump includes a first terminal and a second terminal. The first terminal is configured to receive the first voltage from the solar cell section, and the second terminal is configured to output a second voltage that is higher than the first voltage. An output section is configured to receive an output voltage output by the charge pump circuit. The charge pump circuit is formed on a single semiconductor substrate.

Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.

Abstract: An LED driver includes an embedded non-volatile memory (NVM) capable of being programmed and storing control data for setting a variety of features of the LED driver, such as the maximum current for driving the LEDs, analog parameters such as the resistance of the internal resistor for setting the reference current for the LEDs, and the operation modes of the charge pump of the LED driver. This enables implementation of multiple LED driver product options without the need for different metallization steps during the fabrication process for the LED driver.

Abstract: A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N? type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N? type silicon region and the N+ type silicon region, respectively. The oxide layer has a thickness 0.5 to 3 microns. The power device also includes a polymide layer having a thickness of 3 to 20 microns; a first field plate overlying the oxide layer; and second field plate overlying the polymide layer and the first field plate, wherein the second field plate overlaps the first field plate by 2 to 15 microns.

Abstract: A power device includes a semiconductor substrate of first conductivity having an upper surface and a lower surface. An isolation diffusion region of second conductivity is provided at a periphery of the substrate and extends from the upper surface to the lower surface of the substrate. The isolation diffusion region has a first surface corresponding to the upper surface of the substrate and a second surface corresponding to the lower surface. A peripheral junction region of second conductivity is formed at least partly within the isolation diffusion region and formed proximate the first surface of the isolation diffusion region. First and second terminals are provided.

Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.

Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.