Abstract: A pipelined escape character insertion component sequentially includes a character specific gap inserter and an expansion component. The gap inserter inserts gaps into blocks of data in a received data stream in which data elements within the blocks correspond to control elements. The expansion component receives the blocks of data elements with the inserted gaps and rearranges the gaps to positions adjacent to the data elements that correspond to the control elements. Additionally, an escape character follows the expansion component and inserts escape characters in the inserted gaps.

Abstract: A network device includes redundant buses, redundant master controllers, and slave controllers. Each of the master controllers connects to a corresponding one of the buses. One of the master controllers acts as an active master and the other master controllers act as standby masters. The active master commences a bus cycle that includes an address interval and a data interval, provides a destination address on the corresponding bus during the address interval, and transmits or receives a command or data during the data interval. The slave controllers connect to the bus, detect commencement of the bus cycle, sample the destination address from the bus a predetermined amount of time after commencement of the address interval, and transmit or receive a command or data during the data interval.

Abstract: A compute engine allocates data path bandwidth among different classes of packets. The compute engine identifies a packet's class and determines whether to transmit the packet based on the class' available bandwidth. If the class has available bandwidth, the compute engine grants the packet access to the data path. Otherwise, the compute engine only grants the packet access to the data path if none of the other packets waiting for data path access have a class with available bandwidth. After a packet is provided to the data path, the compute engine decrements a bandwidth allocation count for the packet's class. Once the bandwidth count for each class is exhausted, the compute engine sets each count to a respective starting value-reflecting the amount of bandwidth available to a class relative to the other classes.

Abstract: A system for processing packets of data may include a gather unit configured to gather data elements from a number of non-contiguous locations in a packet of data. The gather unit may place the data elements in a number of contiguous locations in the packet. A processor may be configured to process the data elements from the number of contiguous locations to generate processed data elements. A scatter unit may be configured to scatter the processed data elements to the number of non-contiguous locations in the packet.

Abstract: An ATM switching system 1 is provided with an ATM switch 11, a reserved connection memory 12 for storing reserved connection information, a call history memory 13 for maintaining call histories of requests for connection from subscriber's terminal units 2?1 to 2?n, and a call-signal processing section 15. The call-signal processing section 15 generates a request for connection with respect to a trunk ATM switching network 3 by the use of the call histories in the call history memory 13 in the case where no call was issued from the subscriber's terminal units, and stores response results thereof in the reserved connection memory 16. Thereafter, when there was a call from the subscriber's terminal units 2?1 to 2?n, and contents of the request for connection thereof are the same as the reserved connection information, which has been stored in the reserved connection memory 16, processing for connection is executed by the use of the reserved connection information.

Abstract: The invention relates to systems and methods to validate data in a design document transmitted over a computer network from a design organization to a contract manufacturer for manufacturing a product. The computer implemented system includes computer software for storing a past version of the design document, receiving and storing a new version of the design document, storing a dictionary, comparing the new version to the past version of the design document to detect a change in the data. If there is no change, the program stops. If there is a data change, the software sets the past version to the new version of the design document, and uses the dictionary to correct and validate the data that has changed between the past and new version which results in a design document with data to use for the contract manufacturer only.

Abstract: A system for removing gaps from streams of packets is provided. The system includes a packet splitter, a header buffer, a data buffer, and a packet combiner. The packet splitter receives the packets. Each of the packets includes a packet header and packet data. The packet splitter separates the packet header from the packet data for each of the packets. The header buffer stores the packet headers and the data buffer stores the packet data. The packet combiner reassembles the packets from the packet headers in the header buffer and the packet data in the data buffer and removes gaps from the reassembled packets.

Abstract: In a gateway, a packet received from a first network contains first address data conforming to the first network in the packet header and second address data conforming to a second network in an auxiliary header. The first address data of the packet is then rewritten with the second address data of the packet and transmitted from the gateway to the second network.

Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.

Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.

Abstract: A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.

Abstract: Local concentration of accessing loads on a data buffer during data cell reading is reduced. Also, by providing sufficient time for a data cell reading operation with respect to data cell transmission timing, transmission rate fluctuation of CBR data cells in a transmitting side is reduced. When transmission of a new data stream is added, controller in a cell control unit refers to a transmitted data cell count of VC information processed through a slot immediately before. The controller determines whether a data cell transmitted through the slot immediately before is a head portion of a packet or not. If the data cell transmitted through the slot immediately before is the head portion of the packet, the controller only adds the VC information of the data stream to a shaper link list, and withholds transmission of the data cell.

Abstract: A statistically based counter increments a count value based on a random probability. As the count value increases, the probability of increasing the count value is decreased. The count value is stored as the combination of an exponent and a mantissa. In this manner, the count value can count up to a very large dynamic range while using a relatively small storage area for the count value.

Abstract: A compute engine allocates data path bandwidth among different classes of packets. The compute engine identifies a packet's class and determines whether to transmit the packet based on the class' available bandwidth. If the class has available bandwidth, the compute engine grants the packet access to the data path. Otherwise, the compute engine only grants the packet access to the data path if none of the other packets waiting for data path access have a class with available bandwidth. After a packet is provided to the data path, the compute engine decrements a bandwidth allocation count for the packet's class. Once the bandwidth count for each class is exhausted, the compute engine sets each count to a respective starting value—reflecting the amount of bandwidth available to a class relative to the other classes.

Abstract: To provide a method and network system, wherein the proper VPI values are allocated, after the user devices are connected with the network device. A user device transmits a first specific ATM cell, while a network device receives the first specific ATM cell and transmits toward the user device a second specific ATM cell which carries a proper VPI value in the information field of ATM cell. The proper VPI value in the second specific ATM cell is memorized and used by the user device for its own VPI value for communication.

Abstract: A compute engine's central processing unit is coupled to a coprocessor that includes application engines. The central processing unit initializes the coprocessor to perform an application, and the coprocessor initializes an application engine to perform the application. The application engine responds by carrying out the application. In performing some applications, the application engine accesses cache memory—obtaining a physical memory address that corresponds to a virtual address and providing the physical address to the cache memory. In some instances, the coprocessor employs multiple application engines to carry out an application. In one implementation, the application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Abstract: A coprocessor transfers data between media access controllers and a set of cache memory without accessing main memory. The coprocessor includes a reception media access controller that receives data from a network and a transmission media access controller that transmits data to a network. A streaming output data transfer engine in the coprocessor transfers data from the reception media access controller to cache memory. A streaming input data transfer engine in the coprocessor transfers data from cache memory to the transmission media access controller. The coprocessor's data transfer engines transfer data between cache memory and the media access controllers in a single data transfer operation—eliminating the need to store data in an intermediary memory location between the cache memory and data transfer engines.

Abstract: A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

Abstract: A method for transferring an MPOA packet which is capable of permitting address resolution based on layer 3 packet filter information and capable of preventing establishing an undesirable short cut path. In an ATM network, an MPOA server 20 which received an address resolution request packet from an MPOA client 10 determines whether or not the address resolution request packet be forwarded to the other MPOA server or the other MPOA client based on a layer 3 packet filter information.

Abstract: An asynchronous transfer mode connection band control system in a system for transmitting and receiving an asynchronous transfer mode cell utilizing an asynchronous transfer mode network, has data storage means for storing a connection band of a preferential switched virtual connection having high preference in the asynchronous transfer mode network being stored preliminarily as a band acquiring data and storing acquired band data of a switched virtual connection currently established connection, and connection band control means for performing control of connection band on the basis of a total number of bands derived by a sum of the band acquiring data and the acquired band data stored in the data storage means.