Abstract: A communication node contains intelligence for directing both internet protocol (IP) packets and Asynchronous Transfer Mode (ATM) cells toward their destinations. The ATM cells and IP packets may be received within a common data stream. The respective devices process the ATM cells and IP packets to direct the cells and packets to the proper output ports towards their destinations. The device is capable of performing policing and quality of service (QOS) processing on both the ATM cells and the IP packets.

Abstract: A helical drive system for seating and unseating a removable component, such as a printed circuit board, into a slot is described. The helical drive system includes a receptacle fixed to a housing proximate the slot. A handle and drive shaft are attached to the printed circuit board. The drive shaft has a helical groove that mates with a pin included in the receptacle. Rotation of the drive shaft pulls the printed circuit board into the slot and fully seats the printed circuit board. Rotation in the other direction unseats the printed circuit board. The helical groove has an enlarged entry that terminates in one or more points. This configuration facilitates the automatic alignment of the pin with the helical groove.

Abstract: A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.

Abstract: A transmission source bridge collects packets sent from nodes connected to a serial bus in accordance the IEEE1394 Standards, into one packet in an order they are to be transmitted and then sends them onto an ATM network, so that a transmission destination bridge receives this packet and divides it into a plurality of smaller packets and transfers them, in the order they were sent, to nodes connected to the serial bus in accordance with the IEEE1394 Standards.

Abstract: A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes a streaming input engine for retrieving data from the memory and supplying the data to the set of application engines. In one embodiment, the streaming input engine includes a fetch engine with a memory opcode output and address output for accessing cache memory. The streaming input engine also includes an alignment circuit for buffering and aligning data retrieved from the memory. The alignment circuit includes a data buffer, register, byte selector, and shifter. The data buffer stores data accessed by the fetch engine. The register stores old data from the data buffer's output when the buffer sources new data. The byte selector selects data from the data buffer and the register.

Abstract: A system includes a plurality of processing clusters and a snoop controller. A first processing cluster in the plurality of processing clusters includes a first tier cache memory coupled to a second tier cache memory. The system employs a store-create operation to obtain sole ownership of a full cache line memory location for the first processing cluster, without retrieving the memory location from other processing clusters. The system issues the store-create operation for the memory location to the first tier cache. The first tier cache forwards a memory request including the store-create operation command to the second tier cache. The second tier cache determines whether the second tier cache has sole ownership of the memory location. If the second tier cache does not have sole ownership of the memory location, ownership of the memory location is relinquished by the other processing clusters with any ownership of the memory location.

Abstract: A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a sequencer coupled to a set of application engines for performing operations assigned to the compute engine. The sequencer is coupled to application engines through a set of data, enable, and control interfaces. An arbiter couples the sequencer and application engines to memory. Alternatively, the coprocessor may include multiple sequencers, with each sequencer being coupled to a different set of application engines. One set of application engines includes a media access controller for communicating with a network and a data transfer engine coupling the media access controller to the arbiter. In one implementation, application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Abstract: In a cable modem system, signals are transmitted upstream from a cable modem (CM) to a cable modem termination unit (CMTS) when the subscriber desires to communicate with the headend. The invention described herein is directed to a method and apparatus for increasing the communication channel between the CM and the CMTS. This is accomplished by providing a method and apparatus for increasing physical layer flexibility in cable modem systems. In this manner, the CMTS is capable of assigning burst profiles and granting mini-slots to the CMs according to the CMs' burst profile and robustness level.

Abstract: A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a media access controller engine and a data transfer engine. The media access controller engine couples the compute engine to a communications network. The data transfer engine couples the media access controller engine to a set of cache memory. In further embodiments, a compute engine includes two media access controller engines. A reception media access controller engine receives data from the communications network. A transmission media access controller engine transmits data to the communications network. The compute engine also includes two data transfer engines. A streaming output engine stores network data from the reception media access controller engine in cache memory. A streaming input engine transfers data from cache memory to the transmission media access controller engine.

Abstract: A unicast/multicast system has an internal cell generating section that generates an internal cell to include its output index information based on user data, and an output port conversion table that stores the relation of output index information and output port number for the internal cell in the form of one-to-one for the unicast and one-to-multiple for the multicast.

Abstract: A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first processing cluster forwards a memory request to the snoop controller for access to a memory location. In response to the memory request, the snoop controller places a snoop request on the snoop ring—calling for a change in ownership of the requested memory location. A second processing cluster receives the snoop request on the snoop ring. The second processing cluster generates a response to the snoop request. If the second processing cluster owns the requested memory location, the second processing cluster modifies ownership status of the requested memory location.

Abstract: A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory requests from each processing cluster. The data ring enables clusters to exchange requested information. The snoop ring is coupled to the snoop controller—enabling the snoop controller to forward each cluster's memory requests to the other clusters in the form of snoop requests.

Abstract: A subscriber network system is provided with is capable of reducing the response time and reducing the device cost. In the subscriber network system, a control cell is generated which includes modified information when modification is caused for the filter table 230 of the cell filter 24-1 to 24-n in the ATM concentrator 200. The cell filters 24-1 to 24-n of the ATM concentrator 200 distribute the cells input through the cell inserting and dividing portion 210 to the subscribers. The control cell terminating portion 220 terminates the control cell supplied from the ATM exchange 100. The filter table 230 stores the setting information for the cell filters 24-1 to 24-n in the control cell terminated at the control cell terminated at the control cell terminating portion 220.

Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.

Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.

Abstract: A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.

Abstract: According to one embodiment, an encryption system (500) includes an input buffer (504) that can provide data blocks from different contexts (522-1 to 522-n) to a selected encryption circuit (524-1 to 524-m) according to a scheduling section (502). A scheduling section (502) can include a register array (510) having rows that each correspond to a context and columns that correspond to an encryption circuit. Each register array (510) row can store one “hot” bit that designates a context with a particular encryption circuit. A column can be selected by a multiplexer (514) and its values prioritized and encoded by a priority encoder (518) to generate an address that results in the selection of a data block from a particular context. Priority may be varied by shifting a column value with a rotate circuit (516) according to an offset value (OFFSET).

Abstract: An apparatus includes a compute engine coupled to a first tier cache memory including a data array. The first tier cache receives memory access requests from the compute engine. A second tier cache memory is coupled to the first tier cache to receive memory access requests for memory locations not owned by the first tier cache. To avoid stale data storage, the first tier cache does not load the data array with data returned by the second tier cache under the following condition—the second tier cache returns the data in response to a cacheable load operation from a memory location after the compute engine issues a subsequent store operation to the same memory location.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A debugging and diagnostic system allows a developer to receive low-level diagnostic information from multiple processors in a complex electrical system. A bus connects a master processor to the processors to be debugged via corresponding receiver/driver circuits. The receiver/driver circuits receive serial information from the processors and transmit it to the bus. The master processor controls the receiver/driver circuits through a control logic circuit.