Abstract: A multi-loop phase lock loop (PLL) contains multiple loop filters, each having different bandwidths. The multi-loop PLL receives one of multiple high-frequency clock signals as an input. A phase detector outputs a signal, based on the phase difference between the high-frequency clock signal and a feedback signal to the loop filters. A voltage controlled oscillator generates an output clock signal based on signals received from the loop filters. During a clock switch over sequence between the multiple high-frequency input clock signals, the multi-loop PLL uses one of its loop filters with a wide bandwidth to quickly lock the input clock signal. Once the clock signal is locked, a narrower bandwidth loop filter in the PLL is then used to reduce jitter in the locked signal.

Abstract: A traceless midplane contains substantially no traces, pins, or active components and includes a front portion and a back portion. The front portion includes first connectors. The back portion includes second connectors arranged in a grid pattern. Each of the second connectors includes electrically-conductive conduits that connect the second connector to a corresponding one of the first connectors through the midplane. The second connectors include data connection points, ground connection points, and clock connection points. At least some of the data connection points are separated from each other and from the clock connection points by the ground connection points.

Abstract: A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router.

Abstract: According to one embodiment (300) a ternary CAM can include rules stored in CAM locations, where each rule includes match criteria. CAM locations determine priority among various rules. An input value can be matched against stored rules according to the match criteria. In an update operation (300) the CAM can receive a new rule (302). The new rule can be checked for overlap against currently stored rules (304). Rules overlap if an input value exists that can match both rules. If the new rule does not overlap any other rules, it can be added to any free location in the CAM. If the rule overlaps one or more existing rules, the new rule can be stored in an available location that with the appropriate priority with respect to the stored overlapping rules. If no such available location exists, a new set of CAM locations can be randomly selected, and the new rule and all overlapping rules can be written into the selected locations according to priority value.

Abstract: The invention provides forced-air cooling to components mounted on circuit boards oriented in a side-to-side direction in a system. Airflow may enter and exit the system through the front and back (or vice-versa), rather than the sides of the system. In one embodiment, airflow entering the front of the system is re-directed in an upward direction, then split to form airflow branches traversing in a side-to-side direction. The airflow branches traverse across the surfaces of circuit boards, then are directed in an upward direction and out the back (or front) of the system. The airflow branches preferably move substantially the same volume of air per unit of time.

Abstract: A system and method form searching an associative memory using input key values and first and second hashing sections. Key values (Kn) can be hashed in the first hashing section (102) to generate first output values H1(Kn) that access a first store (104). The first store or memory portion (104) can include “leaf” pointer entries (106-2) and “chunk pointer” entries (106-3). A leaf pointer entry (106-2) points at data associated with an applied key value. A chunk pointer entry (106-3) includes pointer data. If a chunk pointer entry (106-3) is accessed, the key value (Kn) is hashed in the second hashing section (108) to generate second output values H2(Kn) that access a second store or memory portion (110). Second hashing section (108) hashes key values (Kn) according to selection data SEL stored in a chunk pointer entry (106-3).

Abstract: A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.

Abstract: A removable apparatus for carrying a circuit board includes a carrying plate having a notch to receive a stationary pin of an enclosure and a faceplate connected to one end of the carrying plate. A rotating cam connects to the carrying plate and acts on the pin to move the apparatus relative to the pin during insertion into and removal from the enclosure. The cam includes two different surfaces, each of which acts to move the apparatus either into or out of the enclosure. A linkage is connected to the cam and extends through the faceplate, connecting to a lever on the exterior of the faceplate. The lever is used to rotate the cam, which in conjunction with the pin provides translational motion either to mate a connector on the circuit board with a corresponding connector in the enclosure or to separate the mated connectors, depending on the direction of rotation.

Abstract: A method and apparatus for transferring data between a driver and a receiver operating in two distinct clock domains under the control of first and distinct second clock signals. The method includes transferring data out from the driver at an active edge of the first clock signal. A delay after the active edge of the first clock signal that data may be unstable is determined. The reading of data received from the driver at the receiver is delayed until an active edge of the first clock signal is received that is generated after the delay has expired.

Abstract: A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.