Abstract: A system prevents disruption of one or more system buses. The system monitors communication on the one or more system buses during an input mode and an output mode and detects changes between the input mode and the output mode. The system determines whether a predetermined time period has elapsed after a change from the input mode to the output mode and changes from the output mode to the input mode when the predetermined time period has elapsed after a change from the input mode to the output mode.

Abstract: A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

Abstract: A system and method for managing connections between a server and a plurality of clients at a network connection management device is provided. The method comprises maintaining at least one connection to the server, receiving requests from the clients, transmitting the requests to the server, receiving responses to the requests from the server, and monitoring a server response time for a selected request sent to the server, the server response time for the selected request being the time elapsed between transmitting the selected request to the server and receiving a corresponding response from the server. The method may also include basing the number of connections.

Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.

Abstract: Techniques are described for aggregating multiple media packets to improve end-to-end bandwidth efficiency. The techniques include using an RTP aggregation protocol that is not sensitive to packet loss to aggregate multiple media packets under a single header. According to the RTP aggregation protocol, the single header for an aggregated media packet comprises a version field, a zero field, a sequence number field and a trunk ID field. The single header encapsulates the aggregated payload, which is an aggregation of Real-Time Protocol (RTP) segments. An RTP segment either has a compressed format or an uncompressed format. The uncompressed RTP segment includes the complete uncompressed RTP packet copied from the original User Datagram Protocol (UDP) packet. The compressed RTP segment includes the payload of the original RTP rather than the complete original RTP packet.

Abstract: A system for redundancy switching of line cards in a communications system. When a line card needs to be replaced or serviced or becomes inoperable, signal traffic is switched to and through a redundant line card. This is achieved by implementing a switching fabric on I/O cards, where the I/O cards carry signal traffic to and from line cards. The switching fabric enables traffic to and from an I/O card servicing the line card to be replaced to instead service the redundant line card.

Abstract: A method of carrying out arbitration in a packet exchanger including an input buffer temporarily storing a packet having arrived at an input port, and a packet switch which switches a packet between a specific input port and a specific output port, includes the steps of (a) concurrently carrying out a first plurality of sequences in each of the sequences basic processes for at least one of the input buffer and the output port are carried out in a predetermined order, and (b) making an allowance in each of the sequences for packets to be output through output ports at different times from one another.

Abstract: A system for selecting bus mastership in a multi-master system includes master devices and at least one slave device. The master devices generate control signals relating to bus mastership in the multi-master system. The slave device(s) receive the control signals from the master devices, determine whether a conflict exists based on the control signals, generate one or more alternate control signals for selecting bus mastership when a conflict is determined to exist, and select bus mastership using the one or more alternate control signals.

Abstract: A signal conductor includes first and second connectors connected to the ends of a cable. The second connector includes a signal processing element that processes signals transmitted between the first and second connectors. In another implementation consistent with the principles of the invention, the signal processing element is located in a patch panel connected to the signal conductor.

Abstract: Methods and apparatus are provided for tunneling (transparently transmitting) over a packet network, from a source to a destination, the spectrum of one or more bandpass channels individually selected from a larger spectrum at the source. Each channel is selected, translated to baseband (using sampling techniques), digitized, framed, merged with other digital services, transmitted (along with associated attribute information) using packet techniques, and later reconstructed. The present invention provides a selective and efficient use of available bandwidth, in that it is not necessary to transmit the entire spectrum, when only one or few portions of the spectrum are desired. This in turn, reduces bandwidth requirements all along the transmission path and at the source and destination. The reduced bandwidth requirements have associated reductions in power and costs.

Abstract: To provide a switching system with telephone switching function mainly on the basis of hardware processing by using isochronous channel which is a real time communication channel. The switching system comprises a gateway node connected with ISDN (Integrated Services Digital Network) and PSTN (Public Switched Telephone Network), and one or more extension nodes, and a serial bus such as IEEE 1394 bus. The gateway node transforms data rate of outside line into data rate of extension node, and the other way around, and secure a seamless communication channel. Concretely, the gateway node secures an isochronous channel, according to a request from the extension nodes or the outside line, and executes switching such as transfer or reservation. A resource manager holds a table for managing the gateway node and extension node.

Abstract: In an interworking apparatus operable in accordance with a radio protocol of using a plurality of radio channels in parallel and another protocol different from the radio protocol, a plurality of memories store a plurality of frames one by one in correspondence with the plurality of the radio channels, respectively. The memories may be for storing PPP frames and/or radio frames. The interworking apparatus may be included in a mobile station or an interworking facility, such as a base station, a mobile switching center. Without exerting any influence to the other radio channels prior to transmission, reception can be done by using no order control protocol. This is very effective and helpful to improve in the transmission efficiency.

Abstract: In an illustrative embodiment, a desired signal processing transfer function is implemented using a generic pipelined data processor having variable latency followed by a variable latency multistage FIFO. The delay of the multistage FIFO is varied dynamically to keep the number of outstanding samples (and thus the overall latency) a constant. The present invention enables an abstract approach to the design of higher-level signal processing transfer functions while the design of the underlying low-level circuitry is driven solely by target implementation technology issues. Thus, the higher-level design of signal processing transfer functions is decoupled from the low-level (logic and physical) design. Furthermore, test bench modules and vectors for testing the transfer function can also be to be prepared independent of the specifics of the low-level circuitry associated with the target implementation technology.

Abstract: An interconnect network for operation within communication node, wherein the interconnect network may have features including the ability to transfer a variety of communication protocols, scalable bandwidth and reduced down-time. According to one embodiment of the invention, the communication node includes a plurality of I/O channels for coupling information into and out of the node, and the interconnect network includes at least one local interconnect module having local transfer elements for transferring information between the plurality of I/O channels; and scaling elements for expanding the interconnect network to include additional local interconnect modules, such that information can be transferred between the local interconnect modules included in the interconnect network.

Abstract: Transparent wavelength division multiplexing systems and methods include an array of wavelength converters receiving n input signals and shifting the wavelength of each input signal by a different amount so that n different wavelengths result. Each of the wavelength converters shifts the wavelength of the input signal by a known amount. The resulting signals may be combined and transmitted over a fiber. A passive (or active) wavelength splitter may be used to recover the signals from the fiber, and deliver the signals directly to one or more network devices. Receivers in the receiving router or switch generally are not wavelength-specific, so the n optical signals need not be shifted back to a common wavelength prior to the router or switch.

Abstract: A two wire serial bus is connected between different circuit boards in a complex electrical system. The two wire serial bus may be used to receive status information about each of the circuit boards in the system. A master control processor on one of the circuit boards controls which of the other circuit boards are active on the serial bus. Each of the non-master circuit boards includes a series of switches that electrically isolate or connect portions of the two wire serial bus from one another. Through the series of switches, both the master control processor and processors local to each of the other circuit boards may simultaneously access different portions of the serial bus.

Abstract: A scheduler allowing high-speed scheduling scalable with the number of input and output ports of a crosspoint switch and suppressed unfairness among inputs is disclosed. The scheduler includes an M×M matrix of scheduling modules, each of which schedules packet forwarding connections from a corresponding input group of input ports to selected ones of a corresponding output group of output ports based on reservation information. A diagonal module pattern is used to determine a set of M scheduling modules to avoid coming into collision with each other. Each determined scheduling module performs reservation of packet forwarding connections based on current reservation information and transfers updated reservation information in row and column directions of the M×M matrix.

Abstract: A switch/router contains intelligence for more quickly determining a next hop for an network layer packet. A network forwarding lookup table or array structure is configured so as to minimize the number of memory accesses required. This results in a decrease in time due to memory access and a decrease in computational overhead due to the memory accesses. In one embodiment, a first forwarding lookup is indexed by the first 16 bits of a destination address. A second forwarding lookup is indexed by the subsequent 8 bits of the destination address, and a final third forwarding lookup is indexed by the last 8 bits of the destination address. Each entry within a forwarding lookup contains either direction as to how properly forward the packet or reference to a next subsequent forwarding lookup.

Abstract: A cell disposal avoidance system is provided that can avoid disposal of cells resided in the QoS buffer when a traffic of a specified QoS class in an ATM switch increases. The ATM switch includes a storage cell number monitor, a software data section 813, and a software controller 812. The storage cell number monitor monitors congestion of plural QoS buffers in the buffer 3, 5. The software data section 813 stores a cell reading priority (WRR value) attached for each QoS buffer. The software controller 812 dynamically changes the WRR value when congestion of a QoS buffer is in a congestion state (at generation of cell disposal or buffer congestion alarm) and increases the WRR value of the QoS buffer in a cell disposal state. Cells are divided in a time division mode according to the weight of the WRR value and read in a round format from the QoS buffer. The ATM switch resets the WRR value to an initial value when the congestion of the QoS buffer ceases.

Abstract: A packet processing engine includes multiple microcode instruction memories implemented in parallel. For each cycle of the pipeline, an instruction from each of the memories is retrieved based on a program counter. One of the instructions is selected by a priority encoder that operates on true/false signals generated based on the instructions. The selected instruction is executed to thereby perform the packet processing operations specified by the instruction.