Abstract: A network router includes hot-swappable physical interface cards that allow the router to communicate using a variety of network technologies. Power to the interface cards is sequentially ramped to avoid disruptive power surges. The router includes multiple power supplies, a power monitor circuit, power on/off control circuitry, and a controller. The controller detects the presence/absence of the physical interface cards and controls the power monitor circuit and power on/off control circuit to sequentially ramp or sequentially remove power to the physical interface cards.

Abstract: A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.

Abstract: A system having multiple arbiters is constructed to reduce the chances of arbiters synchronizing with one another. Each arbiter includes a random process that introduces randomness into an arbitration scheme performed by the arbiter. Because of the randomness, the arbiters will not tend to synchronize with one another, even when receiving an identical stream of input values.

Abstract: A method and apparatus for performing a lookup in a switching device of a packet switched network where the lookup includes a plurality of distinct operations each of which returns a result that includes a pointer to a next operation in a sequence of operations for the lookup. The method includes determining a first lookup operation to be executed, executing the first lookup operation including returning a result and determining if the result includes a pointer to another lookup operation in the sequence of operations. If the result includes a pointer to another lookup operation, the lookup operation indicated by the result is executed. Else, the lookup is terminated.

Abstract: A system for providing multiple field matching capabilities for network data packets is disclosed. According to one embodiment (700) the system includes a number of prefix engines (704-0, 704-1, 712-0 and 712-1) coupled together in a pipelined fashion. First level prefix engines (704-0 and 704-1) perform longest prefix matching operations on address values (Dest-IP and Src-IP) and provide address equivalence class values (daclass and saclass). The address class equivalence values (daclass and saclass) are combined with port identification values (Dest-Port and Src-Port) and applied to second level prefix engines (712-0 and 712-1) which provide tuple equivalence class values (dtclass and stclass). The tuple equivalence class values (dtclass and stclass) are combined and applied to an output mapping circuit (718) which provides a flow specification value corresponding to each applied set of address (Dest-IP and Src-IP) and port (Dest-Port and Src-Port) values.

Abstract: Systems and methods for network security including a firewall. One firewall includes a firewall engine. The firewall engine includes a first engine including a first set of rules for sorting incoming IP packets into initially allowed packets and initially denied packets. The firewall engine also includes a filter including a second set of rules for receiving and further sorting the initially denied packets into allowed packets and denied packets.

Abstract: A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes a streaming output engine with a storage engine, alignment circuit, and data buffer. The storage engine includes a memory opcode output and memory address output in communication with the memory. The storage engine employs these outputs to access the memory by supplying memory transaction opcodes and memory addresses. The alignment circuit receives data from other application engines in the set of application engines. In operation, the alignment circuit aligns data transfers from an application engine into a data word. The data buffer stores data words from the alignment circuit and transfers them to locations accessed in the memory by the storage engine.

Abstract: A system for processing data includes a first set of cache memory and a second set of cache memory that are each coupled to a main memory. A compute engine coupled to the first set of cache memory transfers data from a communications medium into the first set of cache memory. The system transfers the data from the first set of cache memory to the second set of cache memory, in response to a request for the data from a compute engine coupled to the second set of cache memory. Data is transferred between the sets of cache memory without accessing main memory, regardless of whether the data has been modified. The data is also transferred directly between sets of cache memory when the data is exclusively owned by a set of cache memory or shared by sets of cache memory.

Abstract: SYNC parsing for Cable Modem Clock Synchronization is implemented using software processing with hardware assist in a manner that achieves the cost benefits of software SYNC parsing with the time accuracy of hardware SYNC parsing. Hardware scans for the arrival of new MPEG frames. Whenever any MPEG frame arrives, the MPEG frame is processed to extract MAC packets. If a SYNC packet is discovered during this processing, the software determines the SYNC arrival time, a comparison is made between the time the SYNC arrival time and the SYNC time value, and the software uses the difference to adjust the Cable Modem clock. Implementation variations include different approaches to when timestamps are recorded, the calculation of the SYNC arrival time, the use of software to process the MPEG frame and MAC packets, and the use of software to perform the time comparison.

Abstract: An apparatus and method for distributing data transmission from a plurality of data input queues in a memory buffer to an output. The method includes associating a priority indicator with each data input queue, determining a priority indicator having a highest priority level among the plurality of priority indicators and selecting the data input queue associated with the priority indicator having the highest priority level to transmit to the output.

Abstract: A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

Abstract: A forwarding node decapsulates and encapsulates data. The decapsulation may be performed using pattern matching techniques and the encapsulation may be performed using pattern insertion techniques. The decapsulation and encapsulation are preferably performed by hardware devices such as application specific integrated circuits (ASICs) to enhance the speed of such operations. The decapsulation and encapsulation may be independent of each other and performed on a per virtual circuit basis.

Abstract: A system and method for providing redundant source synchronous communication links. The system includes a redundant source synchronous communications bus coupling a first component and a second component. The first component includes a clock source and one or more data channels where each data channel includes a transmitter. The second component includes redundant termination systems for receiving signals generated in each data channel. The redundant source synchronous communications bus includes a plurality of first, second and third transmission line portions. Each first transmission line portion is coupled to a transmitter in the first component. The bus further includes a like plurality of transistor switches. Each transistor switch includes an input port, two output ports and primary and redundant switches operable for switching a signal received from the first transmission line portion at the input port to either of the two output ports.

Abstract: A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched. When no address is required to be fetched, then data is read from the memory. When an address is required to be fetched, the address is fetched from the memory and data is read from the memory using the fetched address. To facilitate this, notifications may be stored corresponding to the streams and notification pointers may be used to identify ones of the notifications to be processed. A prefetch pointer may also be used to identify a notification with one or more associated addresses to be prefetched.

Abstract: A voltage regulator having a regulator output operating at a predetermined output voltage level is disclosed. The voltage regulator includes a switching regulator that has a first regulated output providing a first output voltage level, where the first output voltage level is approximately equal to the predetermined output voltage. The first regulated output is coupled to the regulator output. The voltage regulator includes a linear regulator that has a second regulated output providing a second output voltage level, where the second output voltage level is less than the first output voltage level.

Abstract: According to one embodiment (100) a system may receive a multi-bit input value (DEST_IP) and split it into a number of portions (L1bits, L2bits and L3bits). A first portion (L1bits) can generate a first address (A1) that accesses a first array (116). A first array (116) can provide output values or second array pointer values. Second array pointer values may be combined with a second portion (L2bits) to generate a second address (A2). A second address (A2) can access a second array (118). A second array (118) can provide output values or third array pointer values. Third array pointer values may be combined with a third portion (L3bits) to generate a third address (A3). A third address (A3) can access a third array (120) which can provide output values.

Abstract: According to one embodiment, the invention is directed to a facility for providing Asynchronous Transfer Mode (ATM) and Internet Protocol (IP) Quality of Service (QoS) features in a digital communication node. The facility includes a plurality of logical input ports, a plurality of logical output ports, ATM switching elements, IP routing elements and QoS elements. The switching and forwarding elements transfer ATM data cells and IP data packets from the logical input ports to the logical output ports. The QoS elements prioritize, schedule and flow control the transfer of data, based at least in part on ATM QoS features associated with the ATM data cells and on IP QoS features associated with the IP data packets.

Abstract: A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks.

Abstract: A data packing system includes a source memory, a destination memory, and a data packer. The source memory stores data in source storage locations. The data includes valid data and invalid data. The destination memory stores at least some of the data from the source memory in destination storage locations. The destination memory stores the valid data in contiguous ones of the destination storage locations. The data packer transmits the valid data from the source storage locations to the contiguous destination storage locations.

Abstract: A space-efficient power supply powers a system and is housed in a small area of the system. The components of the power supply are designed to reduce heat generation and be aerodynamically efficient. Reduced heat generation reduces the need for air space around the power supply for cooling air, thus allowing the power supply to be housed in a small space. And because the components are aerodynamically efficient, space requirements are further reduced. In one embodiment the power supply is used in a system to power secondary power supplies. The secondary power supplies provide isolated power to components of a system, such as a communications system in an equipment box. In another embodiment, the power supply is used in an equipment box to power communications equipment distributed in the equipment box.