Abstract: The present invention has the effect that the users can automatically create a natural picture in the style of painting-like color, as if it is a photograph, by directly manufacturing a terminal of a new communication service with the spread of multi media applications and next-generation intelligence network services, and that a lot of memory is not desired in the computer graphics system having three-dimensional model to express an embossed effect by applying the style having painting-like coloring to two-dimensional model.

Abstract: A parallel input/serial output device for inputting code bits in parallel and outputting the same in serial in a variable-length encoder divides a bit word into one with a sign bit and without a sign bit in a table for a variable-length encoder, sequentially stores the absolute values in the table in case of the bit word with a sign bit, sequentially stores the remaining bits with the most significant bit being stored finally in case of those with a sign bit, sequentially outputs bits from the next one of the most significant bit in serial and outputs the most significant bit as the last bit if the counted value becomes one. Therefore, the size of an internal conversion table can be decreased to a half, thereby reducing the number of used elements. Accordingly, the size of an address decoder can be reduced to a half and the operational speed can be improved.

Abstract: In a wideband amplifier whose bandwidth is increased using a parallel feedback transistors(PFT), capacitive elements are connected between the first and seventh nodes which are emitters of the seventh and eighth transistors which are parallel feedback transistors, and alternating current(AC) grounds, wherein outputs are supplied from the first and seventh nodes, and the emitter follower buffers are coupled to the first and seventh nodes so that a negative feedback current is leaked through the collector parasitic capacitances of emitter follower buffer transistors. The bandwidth of the amplifier is greatly increased without making the circuit complex.

Abstract: A dual port random access memory (RAM) matching circuit for a Versa Module Europe bus (VMEbus) which makes it possible to have a higher capacity when transmitting and receiving data by using a RAM which is possible to bidirectionally access during a communication between processors using a VMEbus of an electronic switching system. The dual port RAM matching circuit includes a dual port RAM for bidirectionally outputting/inputting a data in accordance with an address and a control signal, an address matching unit for selecting first through sixteenth addresses from a local system or first through sixteenth addresses from a VMEbus in accordance with the control signal, and a data matching unit for selecting 0-th through thirty first CPU data or 0-th through thirty first VMEbus data from the local system in accordance with the control signal from the control bus, and for checking a parity during a data transmission and receiving operation.

Abstract: A fuzzy operation apparatus which can supply various fuzzy operators by combining basic operators provided by hardware with microprograms, performs fuzzy operations in parallel by connecting a plurality of fuzzy operation portions using a network, and performs parallel defuzzification of the result of fuzzy operations stored in the fuzzy operation portions throughout the network. The present invention establishes a network between fuzzy operation portions, performs fuzzy operation in parallel at a plurality of fuzzy operation portions, and defuzzifies each element of a fuzzy set dispersed and stored in the fuzzy operation portions such that defuzzification speed is fast. Also, since there is no need for an exclusive defuzzification processor, the cost of the system is low.

Abstract: A data switching device which implement the data exchange between a plurality of terminals connected to the communication network. Even if the circuit connection exists in the relevant input port and the destination port, since the frame is transmitted to the output part through the dual circuit switch path, the intermix mode service is processed in the output and then the effective intermix mode service can be processed. Also, since the same circuit switch is dually used, the high reliability regarding to the switch failure can be obtained.

Abstract: A method for forming a deflection grating is disclosed, includes the steps of: sequentially forming a dielectric layer and photoresist layer on a compound semiconductor substrate, and patterning the photoresist layer through optical holography to expose the dielectric layer; removing a portion of the dielectric layer on which the patterned photoresist layer is not formed, through RIE using the patterned photoresist layer as a mask; anisotropically etching a portion of the semiconductor substrate on which the dielectric layer is not formed, through RIE using the dielectric layer as a mask, to form a deflection grating; and removing the dielectric layer.

Abstract: The Centralized Management System utilizing a Bus Interface Unit comprises a Computer (4z) installing an address Bus (4a), data Bus (4b), and control Bus (4c), a First-Level Station (4Q1) communicating with the Computer (4z) as the First-Level Station (4Q1) is connected to the buses (4a, 4b, 4c) of the Computer (4z), a plurality of second-level stations (4Q2, 4Q3, . . . , 4QM) communicating with the First-Level Station (4Q1) as the second-level stations (4Q2, 4Q3, . . . , 4QM) are connected to the First-Level Station through a Multipoint Bus (4r). Therefore, the Centralized Management System is capable of communicating the Computer with the First-Level Station through a Dual Port RAM (Random Access Memory), intercommunicating a plurality of Second-Level Stations through a Multipoint Interface and Multipoint Bus, and controlling and managing several thousands of Terminals (for example, Public Telephones).

Abstract: An asynchronous transfer mode (ATM) layer function processing apparatus with an enlarged structure is disclosed including: an ATM layer receiving cell processor for storing a cell start signal and cell input data extracted by use of a cell read clock in a buffer when a cell transmissible signal is received from an input signal of a subscriber physical layer function processor, extracting a flag according to the number of stored cells, and performing a multiplexing operation according to a scheduling algorithm using a cell interrupt signal and the extracted flag; a processor interface for forming a cell from data received from a microprocessor, storing the cell in a buffer, generating the cell interrupt signal, and controlling each constituent of the ATM layer function processing apparatus; an ATM layer transmitting cell processor for performing an input cell routing function according to an output port identifier value when a corresponding routing value and a match signal are generated from a connection table

Abstract: A synthesis filter for an MPEG-2 audio decoder comprising a first coefficient ROM for storing cosine matrix coefficients therein, a first queue memory for storing subband data therein, a first MAC unit for performing a matrixing operation by multiplying the subband data stored in the first queue memory by the cosine matrix coefficients stored in the first coefficient ROM, a second queue memory for storing output data from the first MAC unit therein, a third queue memory being copied with the contents of the second queue memory, a second coefficient ROM for storing window coefficients therein, a second MAC unit for synthesizing the contents copied to the third queue memory with the window coefficients stored in the second coefficient ROM to produce audio data, an FIFO memory for storing the audio data from the second MAC unit therein, a D/A converter for converting the audio data stored in the FIFO memory into an analog audio signal and outputting the converted analog audio signal to a speaker, and a controlle

Abstract: A device and a method for performing a denormalization operation to restore channel signals, normalized into specified levels due to a multichannel process in an MPEG-2 multichannel audio decoder, to their original levels. The denormalization device performs the denormalization operation on the basis of one multiplication operation. To this end, the denormalization device comprises a ROM for storing therein denormalization information to be multiplied by data to be denormalized, a multiplier for multiplying the data to be denormalized, by the denormalization information stored in the ROM, and a controller for controlling the ROM and the multiplier.

Abstract: A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two N.times.N matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an N.times.N matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm.

Abstract: An adaptive clock recovery apparatus.

Abstract: A composite network protective/recovering device includes first to fourth input/output (I/O) modules. The first and third I/O modules are operational modules and the second and fourth I/O modules are protective modules. A first span connection group connects the first I/O operational module with the second I/O protective module. A second span connection group connects the third I/O operational module with the fourth I/O protective module to perform span switching. A first bidirectional line switching ring connects the first I/O operational module and the third I/O operational module to form a bidirectional ring which has two lines in each direction. A second bidirectional line switching ring is connected to the first to fourth I/O modules to form transmitting/receiving operational lines which include two lines in each direction and protective lines which include two lines in each direction.

Abstract: A distributed cycle reset protocol used in a system including a plurality of nodes sharing a single medium, which reduces the reset overhead generated due to an increased medium distance and increased transmission rate in accordance with a reset made by the co-operation between two adjacent nodes. The distributed cycle reset protocol includes a distributed medium connection control unit for controlling each of the nodes in such a manner that a node, in which all quotas thereof have been exhausted, is allocated with new quotas to enter a new cell transmission cycle when it receives a reset signal from a lower-order node after transmitting a reset signal to a higher-order node.

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the

Abstract: An improved multifiber optical connector is disclosed which concurrently transmits an optical signal and provides for optical signal transmission with a lower transmission loss.

Abstract: A subscriber input/output device of a high-speed packet switching system with a parallel common bus type is disclosed. The subscriber input/output device uses a coaxial cable to establish a star network of a radius of hundreds of meters, and the star network is arbitrated by a polling method to be used as a near communication network or an internal link network of a large scale communication system. The high-speed performance of 320 Mbps-class with a relatively simple medium access protocol for transmitting data through a common parallel bus is obtained, and broadcasting and multicasting are supported.

Abstract: A method of processing information charge discount rates for service subscribers in a premium-rate service. Information charge discount rate data for each service subscriber is registered and a service subscriber number and a calling number are received from Service Switching Point. The received service subscriber number is designated as an index value of a main table in a service subscriber database and the main table is then retrieved to check whether data corresponding to the designated index value are present in the main table. If the data corresponding to the designated index value are present, a service feature classification data field in the main table is retrieved to check whether the service subscriber has subscribed to a flexible charging-by-day/time service.

Abstract: An apparatus for implementing the integrated function of virtual container-11(VC-11) and tributary unit group-2(TUG-2) is configured to transmit and receive a DS-1 network signal and a TUG-2 system signal through a synchronization process in a synchronous multiplexing structure. Data between a network and a system is converted by using only one Tx buffer and one receiving buffer in a transmitter and a receiver respectively. An input of a Tx FIFO buffer is a DS-1 signal of 1.544 Mbps, and an output thereof is a TU-11 frame of 1.728 Mbps including spaces for a path overhead and a pointer. An input of a RX FIFO buffer is the TU-11 signal of 1.728 Mbps in which the path overhead and the pointer are eliminated, and an output thereof is the DS-1 signal of 1.544 Mbps.