Abstract: An add-drop control apparatus includes first and second data input units for inputting external first and second data signals, respectively, a frame phase arrangement unit for arranging phases of an external add data signal, an add data controller for transferring a first add data signal from the frame phase arrangement unit to a host stage in a selected one of a plurality of operating modes under control of a processor, a drop data controller for transferring selectively first and second drop data signals from the first and second data input units and a local loop back data signal from the add data controller to a tributary stage in the selected operating mode under the control of the processor, first and second data output controllers for transferring selectively first and second remote loop back data signals from the first and second data input units, first and second through data signals from the second and first data input units and second and third add data signal signals from the add data controller ex

Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass f

Abstract: A method for controlling an overload in a hybrid full electronic switching system, capable of maintaining a stable service condition for an overload control interval and realizing a priority control depending on the type of call by sorting an overload occurring in the system into an overload associated with processors adapted to execute services in a centralized manner and an overload associated with processors adapted to execute same services in a distributed manner and thereby automatically calculating numbers of calls to be accepted respectively for control intervals for two kinds of overloads in different control manners. The method includes two different control procedures respectively applied to a case wherein a reduction in overload can be carried out in a processor involving the overload and a case wherein a reduction in overload can be carried out by limiting services to be executed in other processors.

Abstract: A method for controlling an overload of distributed processors of a full electronic switching system, capable of automatically calculating the number of calls to be accepted for a current interval by use of the number of calls accepted for a previous interval and the number of standby processes of a call processing program so that only the number of calls corresponding to the number of services calculated is acceptable, thereby maintaining a stable service condition for an overload control interval, and capable of realizing a priority control depending on the type of call.

Abstract: A multi-bus real-time message transmitter including a buffer memory for temporarily storing transmission messages, each of the transmission messages containing transmission time data designating time that the transmission message is to be sent, a plurality of transceivers connected to a plurality of bus lines, respectively, the plurality of transceivers sensing statuses of the corresponding bus lines, outputting the resultant bus line status data, sending the transmission messages stored in the buffer memory to the corresponding bus lines and sending messages received from the corresponding bus lines to the buffer memory, a timer for generating an interrupt signal at a fixed period and counting real-time, and a protocol processor for determining a network status in response to the bus line status data from the plurality of transceivers, setting a time window whenever the interrupt signal is generated by the timer, the time window having a time width different according to the determined network status, and co

Abstract: A method for manufacturing the semiconductor laser device comprising the steps of sequentially forming an active layer, a photo-waveguide layer, a cladding layer, and an ohmic contact layer on an upper surface of an InP substrate; forming a first patterned dielectric layer on the ohmic contact layer; depositing a patterned photoresist on the ohmic contact layer to define a p- electrode stripe layer; forming the p- electrode stripe layer only on a part of the ohmic contact layer; performing an annealing process; etching back the layers until the photo-waveguide layer is exposed, using the first patterned dielectric layer and the p- electrode stripe layer as an etching mask, to form a ridge; depositing a second dielectric layer on the substrate formed thus; selectively removing the second dielectric layer to form a contact hole on the p- electrode stripe layer; coating a bonding pad metal layer on the second dielectric layer and in the contact hole; and coating an n- electrode metal layer on bottom surface of t

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer

Abstract: The present invention relates to an automatic frequency control device and an automatic gain control device which have the advantage of improving the efficiency of a system with very low signal-to-noise ratio by compensating for frequency error generated at the local oscillator of a satellite or on the receive paths by demodulating the modulated signal continuously sent out from a transmit earth station for transmitting information without using the separate pilot frequency at a receive terminal of a receive earth station and locking at local oscillator of a frequency downconverter to a voltage controlled oscillator tracking an error after detecting a phase error of a carrier by using demodulated data, by compensating the frequency error due to Doppler frequency deviation by locking a local oscillator of a frequency upconverter to a voltage controlled oscillator tracking a phase change according to Doppler frequency deviation included in the clock after recovering the clock from the demodulated data, and by c

Abstract: A single core optical fiber connector is disclosed in which an optical signal transmitting line between optical fibers is maintained or short-circuited with a low power loss by utilizing a sectional contact of a single core optical fiber. An elastic deformation energy of a polymer material is utilized so as to achieve the sectional contact for minimizing the loss, and precisely machined alignment devices are utilized so as to reduce the misalignment between the optical fibers, thereby improving the assemblability and the economy. The optical fiber sections which are lightly ground on a grinding paper are contacted by using a precisely machined alignment device and by utilizing the elastic deformation energy of the elastic ferrule. This contact is maintained by a coupling between a specially designed plug and an adaptor, thereby forming a structure of an optical fiber connector and an alignment device.

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface

Abstract: A circuit for determining whether a digital circuit clock is operating normally. It includes a monitoring clock receiver for receiving a monitoring clock signal, a counter reset generator which generates a first reset signal in response to the monitoring clock signal, and a reset signal receiver for receiving a second reset signal and synchronizing the second reset signal with the monitoring clock signal. The second reset signal is also used to initialize a digital circuit pack upon power-on. The circuit further includes a monitoring counter circuit for sampling and counting a reference clock signal in response to the first and second reset signals to monitor the monitoring clock signal. The reference clock signal has a frequency twice that of the monitoring clock signal. A NAND logic unit is provided for outputting the monitored result in response to an output signal from the monitoring counter circuit so that the user can determine a clock error according to the monitored result.

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG.

Abstract: The present invention provides an apparatus and method for measuring two- dimensional displacement by moire fringes of concentric circle gratings which two-dimensional displacement can be precisely measured by a pair of grating and the measurement resolution can be improved by the image processing using the characteristics of moire fringes without noises.

Abstract: A chip type capacitor with a multi-layer structure comprising a plurality of inner electrodes classified into two groups one being used as parts of signal lines and the other being connected to grounded lines. Each of the inner electrodes for radio frequency passages has a pair of inwardly extending recesses adapted to make current flows generated in the inner electrode by radio frequency noise be opposite to each other. Each of at least two grounded inner electrode pairs is interposed between vertically adjacent inner electrodes used as parts of signal lines. The inner electrodes of each pair are connected to ground terminals, respectively, and have a shape formed by removing one protruded grounding portion from a cross shape.

Abstract: A parallel distributed sample descrambler part for a cell-based ATM physical layer, comprising a PRBS generator for generating an 8-bit random number when being set to any value other than "0" in response to an initial value set signal upon initialization, to execute a generation polynomial for distributed sample descrambling given by x.sup.31 +x.sup.28 +1, and a descrambler for adding 8 bits of reception data to 8 bits of the random number from the PRBS generator, respectively, to perform the descrambling of the reception data and outputting the descrambled data bits. A sample processor extracts two bits for synchronization of the descrambler from the 8-bit random number from the PRBS generator as first and second samples in response to an external sampling clock and an external synchronous clock.

Abstract: A method of processing an intelligent network service call in a service switching point (SSP) which has a DTMF processor and is connected to the originating local exchange/transit exchange to provide an intelligent network service. The SSP receives a digit from the other exchange in a R2MFC signalling mode to process a trunk signal from the other exchange upon generation of a trunk line seizure request from the other exchange. The SSP analyzes the received digit to check whether a call from the other exchange is a normal call or an intelligent network service call in which subscriber's information must be received in the middle of the service. If the call from the other exchange is the intelligent network service call, the SSP collects a calling number and a calling category from the other exchange, releases the R2MFC signalling mode and forms a speech path with the other exchange to communicate directly with a service user.

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

Abstract: A protection module connected between a main distributing frame and an exchange, for protecting a subscriber circuit from an overvoltage or an overcurrent, comprises an overcurrent protecting device 21 connected between an output of the main distributing frame and a tip line of the exchange; an overcurrent protecting device 211 connected between an output of the main distributing frame and a ring line of the exchange; and an overvoltage protecting device 22 connected in parallel between the tip line and the ring line, having an output (GND) line connected to the exchange.

Abstract: A method and apparatus is disclosed for measuring an energy gap of a semiconductor material. The method contains the steps of analyzing a character of a reference semiconductor sample and setting an energy gap pixel value, estimating a transfer function between the pixel value, positioning the sample properly and imaging the spectrum to obtain a live image, storing the live image and scanning the respective pixel values along an x-axis of the image, sequentially comparing the respective pixel value and the energy gap pixel value, reading an x-coordinate of the pixel and converting the wavelength of the pixel to estimate the energy gap.