Abstract: A method for manufacturing self-aligned optic fiber-optic element coupling devices is described.

Abstract: Disclosed is a boost converter using a stress energy reproducing snubber circuit, the converter comprising a first inductor connected between one terminal of an input portion and a first connection point; a first diode connected between said first connection point and one terminal of an output portion; and a switching device connected between said first connection point and the other terminal of said input portion, the other terminal of said input portion being connected to the other terminal of said output portion, and further comprising a second inductor connected between said first connection point and an anode of said first diode; a capacitor connected between said first connection point and a second connection point; a second diode having an anode connected to said second connection point and a cathode connected to a cathode of said first diode; and a third inductor and a third diode connected in series between said second connection point and the other terminal of said input portion, said third inductor

Abstract: A signal multiplexing apparatus using multiconnection, comprising an input signal interface circuit for inputting a DS1 (or DS1E) signal, a video signal and an ATM cell signal, an input signal processing multiport RAM having a plurality of ports for receiving data from the input signal interface circuit, an input signal control circuit for controlling the input signal processing multiport RAM, and an output signal address generation/multiplexing circuit connected to the input signal processing multiport RAM. The output signal address generation/multiplexing circuit reads data from the input signal processing multiport RAM and multiplexes the read data into a desired format.

Abstract: A method for re-synchronizing a variable length code at a high speed by comparing an input bit string with a plurality of synchronous code patterns in a parallel manner using a parallel-processing pattern matching algorithm when a transmission error is involved in the variable length code received in a variable length decoder used in systems using digital signals requiring a fixed length code pattern, such as broad band-integrated service digital network (B-ISDN) terminal, high definition TV, digital TV, multimedia, video TAX, facsimile and etc..

Abstract: An apparatus and a method for detecting scene change using difference of MAD(Mean Absolute Difference), so called dMAD wherein the method for detecting scene change using difference of mean absolute difference(dMAD) between image frames by use of scene change detecting apparatus comprising frame memory, first absolute calculator, accumulator, multiplicator, first latch circuit, second absolute calculator, first comparator, second comparator, selector and second latch circuit, the method comprising the steps of: (A) calculating MAD of the `n`th input image frame and checking whether scene change judgement variable, which is used for current frame according to scene change of previous frame, is `1`; (B) judging scene change only using MAD since current frame corresponds to the second frame of new scene when scene change variable is `1` at said step (a); (C) judging scene change using dMAD as scene change variable when scene change variable is not `1` at said step (a); (D) saving scene change state and MAD of th

Abstract: The present invention relates to a method and system for synthesizing speech utilizing a periodic waveform decomposition and relocation coding scheme. According to the scheme, signals of voiced sound interval among original speech are decomposed into wavelets, each of which corresponds to a speech waveform for one period made by each glottal pulse. These wavelets are respectively coded and stored. The wavelets nearest to the positions where the wavelets are to be located are selected from stored wavelets and decoded. The decoded wavelets are superposed to each other such that original sound quality can be maintained and duration and pitch frequency of speech segment can be controlled arbitrarily.

Abstract: The present invention relates to an output buffer type Asynchronous Transfer Mode(ATM) switch that enables decentralized processing, which simultaneously sends multiple inputted cells to each output line, and makes implementation easy by modularization, and without speed-up, could process high-speed data inputted/outputted through input/output lines by comprising: a Batcher Sorting Network arraying, in the order of output line group number, N(N=2.sup.1, 2.sup.2, . . . , 2.sup.n, n is natural numbers) cells simultaneously inputted through N input lines of the switch; an Expanded Banyan Routing Network outputting cells arrayed in said Batcher sorting Network to the corresponding output line group containing each output line; and an Output Queueing Modules temporarily storing cells, outputted from said Expanded Banyan Routing Network, in the buffer used as a common memory and sending these cells to the final output lines.

Abstract: A buffer apparatus having a low output impedance includes a first transistor having one terminal coupled to a voltage source, the other terminal coupled to an output terminal of the buffer, and a gate which receives an input signal of the buffer; a second transistor having one terminal coupled to the output terminal of the buffer and a gate which receives the input signal of the buffer; a current sensing circuitry, which is coupled to the other terminal of the second transistor, for sensing a current of the second transistor and amplifying an input current which flows to the second transistor; a voltage driving circuitry, which is formed between the output terminal of the buffer and a ground voltage, for decreasing an output voltage of the buffer by passing the current from the output terminal to the ground voltage according to a control signal which is applied to the voltage driving circuitry.

Abstract: A scanning format conversion circuit for performing the mutual conversion between a progressive scanning format and a zig-zag scanning format to read or write N.times.N discrete cosine transform coefficients from or into a memory in a coding process or a decoding process of a video system. The scanning format conversion circuit comprises a pure logic circuit including an up/down counting circuit, a down counting circuit, first to third selection circuits, a comparison circuit, a phase change circuit, and an accumulation circuit. With this construction, the mutual conversion between the progressive scanning format and the zig-zag scanning format is performed on the basis of the rule between the input orders and the actual positions of the discrete cosine transform coefficients. Therefore, the scanning format conversion circuit is capable of simplifying the implementation of ASIC and performing the scanning format conversion operation regardless of a block size.

Abstract: An apparatus for and a method of duplex operation and management for an SMX-1 system, capable of minimizing a failure of the system and ensuring the consistency of data between the contents of database and the data being currently operated by two operation management subsystem modules (OMMs) operated in a fashion that when a failure occurs in one of the OMMs, the other OMM executes the function to be executed by the one OMM. The OMMs are connected to the target system by a highway interface unit and connected to a remote signalling network operations system (SIGNOS) by an X.25 network using a modem, one of the OMMs being in service to execute a management of network resources and a management of states of signalling networks, while the other OMM being standby.

Abstract: An improved motion vector extractor comprising a first pixel delay element for delaying pixel data of the previous frame by a one pixel interval, a second pixel delay element for delaying the pixel data of the previous frame by a horizontal line interval of a seek block, a third pixel delay element for delaying the pixel data of the previous frame by a seek block horizontal line and one pixel interval, an interpolation circuit for combining the pixel data of the previous frame and the delayed pixel data of the previous frame from the first to third pixel delay elements to produce at least one interpolation pixel data positioned between adjacent ones thereof, a fourth pixel delay element for delaying pixel data of the present frame to produce rectangularly arranged pixel data of the present frame, a plurality of MAD detectors, each of the plurality of MAD detectors subtracting a corresponding one of the interpolation pixel data from the interpolation circuit from a corresponding one of the rectangularly arrang

Abstract: A CMOS differential operational amplifier has a fully differential structure to improve the output swing and a cascode amplification structure to improve the operating speed. This amplifier includes: a differential input stage 21 which receives differential input voltage signals and converts the input voltage signals into current signals; a cascode output stage 22 which amplifies the current signals from the differential input stage 21 and converts them into high gain output voltage signals; and a common-mode feedback circuit(CMF) 23 which makes a common-mode voltage signal of the output voltage signals equal to a reference voltage signal. To the output ports of the cascode output stage 22, a load capacitor (C.sub.L) 24 is connected.

Abstract: A simultaneous optical compression and decompression apparatus having a simple symmetrical arrangement including a plurality of optical splitting/combining units capable of achieving simultaneous splitting and combining of optical signals in opposite directions, a plurality of optical delay units each arranged between adjacent ones of the optical splitting/combining units and adapted to delay the time taken for an optical signal to pass therethrough in each of opposite directions by a predetermined time, so as to reproduce the optical signal in accordance with a predetermined rule.

Abstract: A method for controlling an overload of a main processor by assigning to the main processor of a distributed switching system with a hierarchy structure a function of informing associated lower-level processors of an occurrence of the overload, an increase in call suppression, a decrease in call suppression and a release of the overload upon controlling the overload, and assigning to the lower-level processors a function of automatically calculating the number of calls to be processed in response to a demand of the main processor, and controlling traffic affecting the main processor on the basis of the result of the calculation, so as to maintain a stable service condition for the overload control interval.

Abstract: A modulo reduction method using a precomputed table to increase a reduction speed during the execution of ordinary operational processes using computers and comprises a first step which searches out with an index of an upper log.sub.2 t (t.gtoreq.1) bit number and adds the value stored in a table to a lower n(n.gtoreq.512) bit number; a second step, which if the result, obtained from the addition of said lower n bit number to the number searched out from the table at said first step, produces an overflow (1 bit), eliminates said overflow and finishes the execution of an operation; and a third step, which if said overlow does not occur at said second step, adds .sub.N on a modulo N to the result obtained from said first step and finishes the execution of the operation.

Abstract: An apparatus for adjusting the channel width of a multi-channel fiber amplifier light source, including an erbium-doped optical fiber amplifier constructed to generate a spontaneously emitted, amplified noise beam under a condition that no optical signal is applied thereto, the amplifier being used as a light source for wavelength division multiplexing, namely, a fiber amplifier light source. By the angle-turned Fabry-Perot etalon filter and the fiber-optic beam expander, the channel width can be easily controlled without affecting the free spectral range and the power of output light.

Abstract: The Centralized Management System utilizing a Bus Interface Unit comprises a Computer (4z) installing an address Bus (4a), data Bus (4b), and control Bus (4c), a First-Level Station (4Q 1) communicating with the Computer (4z) as the First-Level Station (4Q 1) is connected to the buses (4a, 4b, 4c) of the Computer (4z), a plurality of second-level stations (4Q2, 4Q3, . . . , 4QM) communicating with the First-Level Station (4QI) as the second-level stations (4Q2, 4Q3, . . . , 4QM) are connected to the First-Level Station through a Multipoint Bus (4r). Therefore, the Centralized Management System is capable of communicating the Computer with the First-Level Station through a Dual Port RAM (Random Access Memory), intercommunicating a plurality of Second-Level Stations through a Multipoint Interface and Multipoint Bus, and controlling and managing several thousands of Terminals (for example, Public Telephones).

Abstract: A coin treatment apparatus is disclosed that includes structure for selecting the inserted coins based upon their size, in accordance with their specific currency units, and transferring the coins to a receiving space. Once in the receiving space, coins of the correct currency unit are moved to their respective receiving containers within a receiving box. Coins that are not of the correct currency unit are transferred to a separate receiving space and discharged from the apparatus.

Abstract: A mobile communication method is disclosed, and particularly a power of two length pseudorandom noise sequence generator is disclosed, in which a pseudorandom noise code sequence is generated to use it for a direct sequence spreading of communication signals in a spread spectrum communication system. In the PN sequence generator, a mask value and a comparison value are calculated for shifting the PN sequence output having a length of 2.sup.N as much as wanted, so that the PN sequence can be shifted as much as a predetermined value in response to the single clock signal. In order to generate a PN sequence of the desired timing, a new PN mask value is directly obtained from the current PN mask value and the offset shift value to be shifted, and at the same time, a comparison value corresponding to the mask value is obtained, whereby ultimately a PN sequence having a length of 2.sup.N after shifting the cycle as much as the desired shifting value is obtained.

Abstract: A bit allocation method for controlling a transmission rate of a video encoder having an intra mode, a predicted mode and a bidirectionally predicted mode. If the intra mode is selected, it is checked whether a scene change indicating signal is outputted. If the scene change indicating signal is not outputted, a bit amount corresponding to the intra mode is allocated to video data and the video data is coded in the intra mode. If the scene change indicating signal is outputted, a bit amount corresponding to the predicted mode is allocated to the video data, the scene change indicating signal is initialized and the video data is coded in the predicted mode. If a scene change is not present in the case where the predicted mode is selected, the bit amount corresponding to the predicted mode is allocated to the video data and the video data is coded in the predicted mode.