Abstract: A structurally improved rail-type device for mechanically splicing optical fibers while reducing the splicing loss is disclosed. The above splicing device not only has a cladding clamp with a seesaw structure thereby easily splicing the optical fibers, it also separately moves the covers relative to the body to easily perform the tuning operation. Due to coating clamp's protrusions and body's slots engaging with each other, the coating clamp exclusively vertically move relative to the body and prevent the optical fibers from being axially thrust. The splicing device further seperately clamps the coating and cladding parts of the optical fibers, thereby preventing the spliced fibers from breaking due to tensile or torsional force. The sliding motion of the covers relative to the body is achieved by the rails of the covers and rail grooves of the body.

Abstract: A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal.

Abstract: An operational transconductance amplifier with a good linearity, comprising a first MOS transistor having its one terminal connected to a ground voltage source and its gate terminal for receiving a circuit input voltage, a second MOS transistor having its one terminal connected to the other terminal of the first MOS transistor and its other terminal connected to a supply voltage source, a reference voltage generator for generating a reference voltage, and an operational amplifier having its negative input terminal connected to a junction between the first and second MOS transistors, its positive input terminal connected to an output terminal of the reference voltage generator and its output terminal connected to a gate terminal of the second MOS transistor. The first MOS transistor acts to convert the input voltage into an output current. The second MOS transistor acts to transfer current flowing through the first MOS transistor to its output terminal.

Abstract: A high-power factor series resonant rectifier circuit comprising a first rectifier for rectifying an AC input power, a push-pull switching circuit for changing a polarity in the output of the first rectifier in response to a resonant frequency, an isolation transformer for transforming the output of the push-pull switching circuit, an LC resonance tank for resonating the output of the isolation transformer, a second rectifier for rectifying the output of the LC resonant tank, and a boost chopper switch connected in parallel to the output of the second rectifier. The boost chopper switch performs a switching operation when a resonant current becomes zero, resulting in an increase in power density. The increase in power density results in a reduction in switching loss. Therefore, the rectifier circuit of the present invention is operable at a high frequency.

Abstract: A connectionless server for an ATM network carries out routing so that connectionless data generated in a local area network or a terminal is delivered to the appropriate destination. The connectionless server includes a cell header processor for delivering a destination address and an HCT (Header Conversion Table) write address to a destination address processor whenever a BOM or SSM cell is received, and for delivering the cell and an HCT read address to a header conversion processor whenever any cell is received. The destination address processor performs searching and delivers header conversion information (VPIo/VCIo/MIDo) generated from the destination address. The header conversion processor stores the header conversion information from the destination address process and converts the header value of the cell input from the cell header processor using header conversion information stored in a header conversion table.

Abstract: The present invention relates to a wavelet transform processor, and more particularly, to a wavelet transform processor using a pipeline with a bit unit, capable of being effectively used in the video processing field, the video compressing field, the video communications field, the computer vision field, and the like, by executing a high speed wavelet transform through a pipeline with a bit unit. The present invention is to provide a wavelet transform processor using a pipeline with a bit unit, which has a low complexity in circuit, high operating speed and a flexibility.

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxi

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the bas

Abstract: The present invention relates to a circuit for searching a fault location in a device having a number of ASIC's, including a first BIP(Bit Interleaved Parity) generating unit, which is coupled to the input stage of the ASIC where a fault will be detected, for calculating and outputting BIP for the specific byte, which is one of overhead bytes that were already utilized, i.e.

Abstract: An apparatus for estimating a half-pel motion comprising: a memory for storing motion-compensation errors in integer-pel positions; an address generator for generating an address of the integer-pel positions to the memory; an operator for receiving the motion-compensation errors from the memory, and calculating motion-compensation errors in the eight half-pel positions which are on the outskirts of the integer-pel position having a minimum motion-compensation error; and a comparator and half-pel motion vector selector for comparing the motion-compensation errors in the eight half-pel positions with the minimum motion-compensation error in the integer-pel position and selecting a position having a minimum motion-compensation error as a final half-pel motion vector.

Abstract: A digital automatic gain controller for a satellite transponder, comprising an amplification circuit for amplifying a radio frequency signal detected by a detector diode by a difference between the detected radio frequency signal and a temperature compensation signal, a microprocessor for inputting an output signal from the amplification circuit and outputting the inputted signal as a telemetry signal to the earth control station, the microprocessor adjusting an output level of a radio frequency channel in response to a telecommand signal from the earth control station based on the telemetry signal, and a conversion circuit for converting an output data signal from the microprocessor into a drive current for driving a PIN diode attenuator. According to the present invention, the digital automatic gain controller is capable of performing an automatic gain control operation flexibly and reliably on the basis of a program.

Abstract: A fuzzy computer which provides high speed fuzzy processing by executing fuzzy information processing in parallel. The fuzzy computer operates according to programs and data downloaded from a host system, and executes fuzzy information processing in parallel to process this information at high speed. The fuzzy computer comprises a single fuzzy processing controller which downloads and designates to control memory operational programs from the host system, starts fuzzy operations according to signals inputted to an instruction register, and informs the host system of its processing status through a status register. A plurality of fuzzy processing elements are connected in parallel to the single fuzzy processing controller through system buses, download fuzzy data from the host system to each built-in knowledge base and perform respective functions in parallel according to control signals from the single fuzzy processing controller.

Abstract: A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

Abstract: A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Abstract: Disclosed is a method for fabricating an optical integrated circuit capable of obtaining a current confinement and a maximum opto-coupling efficiency by using a simple process, in a case where an active device such as an optical waveguide and an optical amplifier. The method comprises a step for growing layers constituting the optical device over an InP substrate, a step for etching the grown layers by use of a wet etching method or a dry etching method of RIE along a plane perpendicular to a (001) plane, and a step for growing a core layer and a clad layer of the waveguide to be optically connected by use of a molecular organic chemical vapor deposition.

Abstract: A method for controlling an operation and management subsystem in a signalling message exchange No.1 system, the operation and management subsystem including a user interface subsystem, a target interface subsystem, an operation control subsystem, a signalling network operation system interworking subsystem, an operation and management subsystem management subsystem and a data management subsystem.

Abstract: A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Abstract: The present invention relates to a method for fabricating the plane waveguide path type of the heater buried optical switch, and it exposes the thin film heater removing the second clad layer to speed the heat radiation of the thin film heater by forming flatly the first clad layer having the thin thickness of about 5-10 .mu.m on the channel waveguide path on which the channel waveguide path is formed on the lower clad layer, and forming the second upper clad layer in the thickness of about 15-20 .mu.m on the first clad layer and the thin film heater after the thin heater having the line width of about two times as compared with these of the channel waveguide path is formed at the channel waveguide path and the corresponding portion on the first upper clad layer.

Abstract: An optical exchanging apparatus is disclosed including N optical transmitters for generating optical signals each having a single constant mode, N mode converters for converting modes of the optical signals generated from the optical transmitters according to a mode-converting signal, an Nx1 coupler for coupling the mode-converted optical signals generated from the mode converters to be supplied to one terminal, a 1xN distributor or distributing the coupled optical signal generated from the Nx1 coupler to N optical signals each having various modes, N mode selectors for respectively passing only the optical signal of a selected mode out of the N optical signals generated from the 1xN distributor, and N optical receivers for receiving the optical signals generated from the mode selectors.

Abstract: To provide a high speed traffic statictics processing apparatus using memory so that a statistical processing for an enormous amount of measured data can be executed in real time by manipulating partially the measured data and storing the partially manipulated measured data using memory and a simple circuit, not transferring the enormous amount of measured data directly to a statistical processor, the present invention comprises a measurement traffic extractor for discriminating the measured traffics from other traffics and extracting the measured traffics, a traffic manipulator for manipulating the extracted traffics, a traffic statistical processor for executing the statistical processing of the manipulated traffic, a traffic dispaly for displaying the data which traffics are processed for and an application processor for requesting for the traffic measurement and controlling their overall operation.