Abstract: An avalanche photodiode in which a strained superlattice structure is used as a multiplication layer, comprising: an n.sup.+ type InP substrate; an n.sup.+ type InP epitaxial layer formed on a main surface of the substrate; an N type In.sub.1-x Al.sub.x As layer formed on the epitaxial layer; an n.sup.+ type In.sub.1-x Al.sub.x As layer formed on the N type In.sub.1-x Al.sub.x As layer, the n.sup.+ type In.sub.1-x Al.sub.x As layer having a relatively high impurity concentration more than the N type In.sub.1-x Al.sub.x As layer; the multiplication layer deposited on the n.sup.+ type In.sub.1-x Al.sub.x As layer, the multiplication layer having an In.sub.0.53 Ga.sub.0.47 As/In.sub.1-x Al.sub.x As superlattice structure; first and second p.sup.+ type In.sub.1-x Al.sub.x As layers laminated sequentially on the multiplication layer; an absorbing layer formed on the second p.sup.+ type In.sub.1-x Al.sub.x As layer, the absorbing layer being made of an In.sub.0.53 Ga.sub.0.

Abstract: A rotation and alignment device for assembling of an optical fiber connector with a lower connection loss. This device image-processes the distribution of optical intensity of light emitted from an end surface of an optical fiber of a ferrule and derives an optical peak intensity point of the end surface of the optical fiber such that the point is placed in a predetermined region of a rectangular coordinate system. This device comprises a rotation and marking part for controlling a rotational position of a marker with respect to the ferrule and marking the optical peak intensity point on an outer surface of the ferrule. A ferrule fixture part is coupled to the rotation and marking part and fixes the ferrule such that the outer surface of the ferrule is marked with the optical peak intensity point by the marker. A vertical supporting part supports the rotation and marking part and the ferrule fixture pat.

Abstract: A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.

Abstract: An internal routing method in an internal network for improving signaling message processing capability by balancing the workload among message handling processors (MHP) in common channel signaling system used in electronic exchanges. An internal routing algorithm is provided in the internal network to balance the workload among MHP's based on the characteristics of a circuit identification code (CIC). An identifying trunk circuit is uniformly distributed, and a load unbalancing factor is formulated approximately as a function of the number of failed MHP's as a worst case. With this approach, all MHP's are loaded almost equally regardless of the number of failed MHP's.

Abstract: A method for approximately matching a DTMF input character string with a key word and for vocally outputting information in response to the input character string. A telephone apparatus is provided to transmit a dual tone multi-frequency (DTMF) signal by utilizing a character panel including a plurality of DTMF buttons which are arranged in order therein. An exchange apparatus intermediates the DTMF signal. A DTMF receiver apparatus converts the DTMF signal into a corresponding digital signal. A service provider terminal apparatus inputs a plurality of key words corresponding to each service name and information data to be provided. A key word storage apparatus includes a service name file unit for storing a service name file, and a key word dictionary unit for storing a key word dictionary. A text information storage apparatus stores a plurality of information data corresponding to each service name.

Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

Abstract: A phase comparing and CMI/NRZ decoding apparatus for accomplishing bit synchronization of CMI data by producing rising transition or falling transition of the clock pulse at the center of unit bit interval of incoming CMI data, by use of the clock pulse having a period equivalent to 2 unit bit intervals of CMI data, and for realizing stable decoding of CMI data to NRZ data. This apparatus is implemented by means of a data output means 2, a clock pulse generating means 1 for generating in-phase and inverse-phase pulses, a inter-transitions time interval information output means 3 for outputting information about line interval between the data transition and the clock pulse transition, a reference pulse generating means 4, a falling transition detecting and 3-step half-period shifting means 6, a rising transition detecting and 2-step half-period shifting means 5, a CMI/NRZ decoding circuit 7 and a code violation detecting means 8.

Abstract: A status management method of this invention comprises: a first step of receiving a status alteration information of speech path device, analyzing each alteration status, and altering a count for each status; a second step of calculating a service reference value of each signalling service device as based on the number of subscriber lines for normal service in case that a status alteration device is subscriber line, and reporting a fault segregating limitation value of each signalling service device in case that said service reference value is altered; and a third step of analyzing a service status of each signalling service device according to said service reference value, and ending the status management on outputting a software alarm according to an analysis result of said service status.

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

Abstract: An automatic power breaking circuit for a communication equipment, for breaking automatically electric power in the communication equipment when the communication equipment does not perform transmission and reception for talk. The present circuit comprises a call processing tone detector 1 connected to a receiving stage of the communication equipment, for detecting a plurality of predetermined tones provided from a switch board of an exchange, a JK flip-flop 2 connected to said call processing tone detector 1, for receiving a source voltage, a talk terminal 4 for receiving said source voltage and being manually switched to an ON state by the user when transmission or reception is required, a D flip-flop 6 connected to said talk terminal 4, an AND gate 7 connected to output terminals of said JK flip-flop 2 and D flip-flop 6, and a transistor 8 connected to an output terminal of said AND gate 7w for switching power being supplied to a transmitting stage of the communication equipment.

Abstract: The present invention provides a phase detector comprising a driver U1 and D-type flip-flops U2 and U3 which reduces the high frequency component of the jitter in VCO, in analog-fashion operation, enables the use of general purpose logic elements being irrespective of the data bit speed, and enables the application of both analog PLL and digital PLL.

Abstract: The present invention comprises a system bus performing control and data transmission function among modules, a system control means, connected to the system bus, performing system control and interrupt control function, a modem and DTMF signal processing means, connected to the system bus, performing modulation and demodulation in the transmission rate of 9,600 bps, 4,800 bps, and 2,400 bps, and transmission and reception of DTMF signal, a standard telephone line connection means connecting the modem and DTMF signal processing means and a telephone to a standard telephone line, a program ROM, connected to the system bus, storing a program which controls communication through the modem and DTMF signal processing means, and a RAM, connected to the system bus, retaining current data.

Abstract: A voice information system utilizing approximately matched input character string and key word and a method for the approximate matching thereof is disclosed. A telephone apparatus is provided to transmit a dual tone multi-frequency (DTMF) signal by utilizing a character panel including a plurality of buttons which are orderly arranged therein. An exchange apparatus is provided to intermediate the DTMF signal. A telephone line matching apparatus is connected from the exchange apparatus to detect a line status of the system and protect the system from an instantaneous higher voltage. A DTMF receiver apparatus converts the DTMF signal into a corresponding digital signal. A service provider terminal apparatus is provided to input a plurality of key words corresponding to each service name and information data to be provided. A key word storage apparatus includes a service name file unit for storing a service name file, and a key word dictionary unit for storing a key word dictionary.

Abstract: The present invention provides a duplex structure signal transfer point system for common channel signaling system No. 7, which includes a serial duplexed interconnection device; a duplexed network interface connected to the serial duplexed interconnection device, for performing an interconnection between signal message processing submodules; a parallel duplexed interconnection device connected to the duplexed network interface, for performing a parallel duplexed interconnection between unit level 2s and a duplexed unit level 3, wherein the duplexed unit level 3 is connected to the parallel duplexed interconnection device, for performing a protocol level 3 of a message transfer protocol in the common channel signalling system No. 7; and wherein the unit level 2s are connected to the parallel duplexed interconnection device, for performing a protocol level 2 of the message transfer protocol in the common channel signalling system No. 7.

Abstract: An output circuit for a bipolar complementary metal oxide semiconductor. The circuit is formed by coupling P channel and N channel metal oxide semiconductor transistors to bipolar transistors to obtain both a low logic level state of 0 volts and a high logic level state of 5 volts.

Abstract: A tri-state logic circuit of a BiCMOS having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching charaacteristic is disclosed. The circuit comprises PMOS transistors M1,M5 and NMOS transistors M2,M3,M4,M6,M7,M8,M9 and bipolar transistors Q1,Q2 and a capacitor C1.