Abstract: Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.

Abstract: In an example, a showerhead pedestal assembly for a substrate processing chamber is provided. The showerhead pedestal assembly includes a faceplate. A platen is disposed within the faceplate and includes a heater element extending through at least one groove in the faceplate. The at least one groove is profiled to accept at least one portion of the heater element. A periphery of the platen is joined to an interior surface of the faceplate by a friction stir welded joint.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, including providing a first substrate to a first station in a semiconductor processing chamber, providing a second substrate to a second station in the semiconductor processing chamber, concurrently depositing a first bow compensation layer of material on the backside of the first substrate at the first station and a first bow compensation layer of material on the backside of the second substrate at the second station, and depositing a second bow compensation layer of material on the backside of the first substrate, while the first substrate is at the first station and the second substrate is at the second station, and while not concurrently depositing material on the backside of the second substrate.

Abstract: Dry development of resists can be useful, for example, to form a patterning mask in the context of high-resolution patterning. Dry development may be advantageously accomplished by a method of processing a semiconductor substrate including providing in a process chamber a photopatterned resist on a substrate layer on a semiconductor substrate, and dry developing the photopatterned resist by removing either an exposed portion or an unexposed portion of the resist by a dry development process comprising exposure to a chemical compound to form a resist mask. The resist may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film EUV resist.

Abstract: A temperature-controlled pedestal includes a pedestal, a temperature sensor to sense N temperature in N zones, and N temperature control devices arranged in the N zones, respectively. A voltage source selectively supplies power to the N temperature control devices. A controller is configured to cause the voltage source to control a temperature in the N zones by a) determining a hottest one of the N zones based on the N temperatures; b) if the hottest one of the N zones is not already cooling, increasing cooling to the hottest one of the N zones using one of the N temperature control devices; c) decreasing cooling to the N zones when a temperature of the N zones is less than a first temperature setpoint; and d) repeating a) to c) until all of the N zones have a temperate less than or equal to the first temperature setpoint.

Abstract: A method for achieving uniformity in an etch rate is described. The method includes receiving a voltage signal from an output of a match, and determining a positive crossing and a negative crossing of the voltage signal for each cycle of the voltage signal. The negative crossing of each cycle is consecutive to the positive crossing of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the plurality of bins associated with the positive crossing and one or more of the plurality of bins associated with the negative crossing, the method includes adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate.

Abstract: A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.

Abstract: A direct drive system for providing RF power to a component of a substrate processing system includes a direct drive circuit including a switch and configured to supply RF power to the component. A switch protection module is configured to monitor a load current and a load voltage in a processing chamber, calculate load resistance based on the load current and the load voltage, compare the load resistance to a first predetermined load resistance, and adjust at least one of an RF power limit and an RF current limit of the direct drive circuit based on the comparison.

Abstract: A plenum for a dielectric window of a substrate processing system includes a first inlet port, a second inlet port, and a body. The body includes: a first recessed area configured to hold a first coil; a second recessed area configured to hold a second coil; a third recessed area configured to oppose a first area of the dielectric window, receive a first coolant from the first inlet port, and direct the first coolant across the first area to cool a first portion of the dielectric window; and a fourth recessed area configured to oppose a second area of the dielectric window, receive a second coolant from the second inlet port, and direct the second coolant across the second area to cool a second portion of the dielectric window.

Abstract: Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: Methods for selective inhibition control in semiconductor manufacturing are provided. An example method includes providing a substrate including a feature having one or more feature openings and a feature interior. A nucleation layer is formed on a surface of the feature interior. Based on a differential inhibition profile, a nonconformal bulk layer is selectively formed on a surface of the nucleation layer to leave a region of the nucleation layer covered, and a region of the nucleation layer uncovered by the nonconformal bulk layer. An inhibition layer is selectively formed on the covered and uncovered regions of the nucleation layer. Tungsten is deposited in the feature in accordance with the differential inhibition profile.

Abstract: Described herein is a pedestal assembly comprising a platen and a sensor support plate below the platen. In at least one implementation, sensor support plate comprises a sensor compartment and a waveguide temperature sensor within the sensor compartment. In at least one implementation, waveguide temperature sensor comprises a temperature sensor comprising a first reflector structure and a second reflector structure. In at least one implementation, first reflector structure and second reflector structure are separated by a gauge length.

Abstract: Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.

Abstract: A method is provided. A substrate situated in a chamber is exposed to a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate and form a modified surface. The substrate is exposed to an activated activation gas to etch at least part of the modified surface.

Abstract: Non-elastomeric, non-polymeric, non-metallic membrane valves for use in high-vacuum applications are disclosed. Such valves are functional even when the fluid-control side of the valve is exposed to a sub-atmospheric pressure field which may generally act to collapse/seal traditional elastomeric membrane valves.

Abstract: A method for applying RF power in a plasma process chamber is provided, including: generating a first RF signal; generating a second RF signal; generating a third RF signal; wherein the first, second, and third RF signals are generated at different frequencies; combining the first, second and third RF signals to generate a combined RF signal, wherein a wave shape of the combined RF signal is configured to approximate a sloped square wave shape; applying the combined RF signal to a chuck in the plasma process chamber.

Abstract: Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.

Abstract: In some examples, a method of processing a substrate comprises applying a photoresist (PR) onto a surface of the substrate, pre-exposing the PR to ultra violet (UV) light before depositing or etching a metal oxide (MO) layer onto the PR, and depositing or etching a MO layer onto the PR subsequent to pre-exposing the PR to UV light.