Abstract: Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

Abstract: Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.

Abstract: A method for etching at least a portion of a layer based on a III-N material includes exposing a least one portion of an upper face of the III-N layer to a plasma treatment with bias voltage pulsing based on chlorine, wherein the plasma treatment is configured to present a duty cycle comprised between 20% and 80%. A first non-zero polarization bias is applied to the substrate during Ton, and a second polarization bias lesser than the first non-zero polarization bias or no polarization bias is applied, during Toff, so as to etch the portion of the III-N layer. The duration of the etching is significantly reduced to obtain a satisfying quality of the III-N layer for the operation of a microelectronic device, such as a transistor or a diode.

Abstract: Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrodeposition of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

Abstract: A method for calibrating a gas flow metrology system for a substrate processing system includes a) measuring temperature using a first temperature sensor and a reference temperature sensor over a predetermined temperature range and determining a first transfer function; b) measuring pressure using a first pressure sensor and a reference pressure sensor over a predetermined pressure range using a first calibration gas and determining a second transfer function; c) performing a first plurality of flow rate measurements in a predetermined flow rate range with a first metrology system and a reference metrology system, wherein the first metrology system and the reference metrology system use a first orifice size and the first calibration gas; and d) scaling temperature and pressure using the first transfer function and the second transfer function, respectively, and determining a corresponding transfer function for the first calibration gas based on the first plurality of flow rate measurements.

Abstract: A thermal choke rod connecting a radio frequency source to a substrate support of a plasma processing system includes a tubular member having a first connector for connecting to an RF rod coupled to the substrate support and a second connector for connecting to an RF strap that couples to the RF source. A tubular segment extends between the first and second connectors. The first connector has a conically-shaped end region that tapers away from the inner surface thereof to an outer surface in a direction toward the tubular segment, and slits that extend for a prescribed distance from a terminal end of the first connector. The outer surface of the tubular segment has a threaded region for threaded engagement with an annular cap that fits over the first connector and reduces an inner diameter of the first connector upon contact with the conically-shaped end region of the first connector.

Abstract: Metal films, such as molybdenum films are deposited on a semiconductor substrate having one or more recessed features in a deposition process modulated by addition of a halogen-containing compound (e.g., an alkyl halide). In some implementations, a pre-treatment of a substrate with a halogen-containing compound is performed prior to contacting the substrate with a metal-containing precursor and a reducing agent. In some embodiments, the pre-treatment is performed such that the halogen-containing compound modifies the surface of the substrate to a greater degree in a field region of the substrate and near the opening of the recessed feature, as compared to the bottom portion of the recessed feature, where the modification of the substrate inhibits deposition of the metal. As a result, deposition of metals with improved step coverage can be achieved. In some implementations, modulation of deposition by halogen-containing compounds is used to achieve bottom-up metal growth in recessed features.

Abstract: In some examples, a magnetic shield for a plasma source is provided. An example magnetic shield comprises a back-shell. The back-shell includes a cage defined, at least in part, by an arrangement of bars of ferro-magnetic material. The cage is sized and configured to at least extend over a top side of an RF source coil for the plasma source.

Abstract: A method for adjusting a height of an edge ring arranged around an outer portion of a substrate support includes receiving at least one input indicative of one or more erosion rates of the edge ring. The at least one input includes a plurality of erosion rates for respective usage periods of a substrate processing system. The method further includes determining at least one erosion rate of the edge ring using the plurality of erosion rates for the respective usage periods, monitoring an overall usage of the edge ring and storing the overall usage of the edge ring in a memory, calculating an amount of erosion of the edge ring based on the determined at least one erosion rate and the overall usage of the edge ring, and adjusting the height of the edge ring based on the calculated amount of erosion to compensate for the calculated amount of erosion.

Abstract: A bottom ring is configured to support a moveable edge ring. The edge ring is configured to be raised and lowered relative to a substrate support. The bottom ring includes an upper surface that is stepped, an annular inner diameter, an annular outer diameter, a lower surface, and a plurality of vertical guide channels provided through the bottom ring from the lower surface to the upper surface of the bottom ring. Each of the guide channels includes a first region having a smaller diameter than the guide channel, and the guide channels are configured to receive respective lift pins for raising and lowering the edge ring.

Abstract: An electrostatic chuck for a substrate processing system is provided and includes a baseplate, an intermediate layer disposed on the baseplate, and a top plate. The top plate is bonded to the baseplate via the intermediate layer and is configured to electrostatically clamp to a substrate. The top plate includes a monopolar clamping electrode and seals. The monopolar clamping electrode includes a groove opening pattern with coolant gas groove opening sets. The seals separate coolant gas zones. The coolant gas zones include four or more coolant gas zones. Each of the coolant gas zones includes distinct coolant gas groove sets. The top plate includes the distinct coolant gas groove sets. Each of the distinct coolant gas groove sets has one or more coolant gas supply holes and corresponds to a respective one of the coolant gas groove opening sets.

Abstract: Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.

Abstract: Provided herein are methods of depositing tungsten (W) films without depositing a nucleation layer. In certain embodiments, the methods involve depositing a conformal reducing agent layer of boron (B) and/or silicon (Si) on a substrate. The substrate generally includes a feature to be filled with tungsten with the reducing agent layer conformal to the topography of the substrate including the feature. The reducing agent layer is then exposed to a fluorine-containing tungsten precursor, which is reduced by the reducing agent layer to form a layer of elemental tungsten. The conformal reducing agent layer is converted to a conformal tungsten layer.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Vapor accumulator reservoirs for semiconductor processing operations, such as atomic layer deposition operations, are provided. Such vapor accumulator reservoirs may include a perimeter plenum volume filled with an inert gas, which may reduce or prevent the leakage of external contaminants into a process gas. In some implementations, the reservoir may be constructed from corrosion-resistant materials to reduce internal contaminants into the process gas.

Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.

Abstract: An edge ring is configured to be raised and lowered relative to a substrate support, via one or more lift pins, in a substrate processing system. The edge ring is further configured to interface with a guide feature extending upward from a bottom ring and/or a middle ring of the substrate support during tuning of the edge ring. The edge ring includes an upper surface, an annular inner diameter, an annular outer diameter, a lower surface, and an annular groove arranged in the lower surface of the edge ring to interface with the guide feature. Walls of the annular groove are substantially vertical.

Abstract: A method is provided and includes: determining a temperature distribution pattern across a substrate or a support plate of a substrate support; determining, based on the temperature distribution pattern, a number of masks to apply to a top surface of the support plate, where the number of masks is greater than or equal to two; and determining patterns of the masks based on the temperature distribution pattern; and applying the masks over the top surface. The method further includes: performing a first machining process to remove a portion of the support plate unprotected by the masks to form first mesas and first recessed areas between the first mesas; removing a first mask from the support plate; performing a second machining process to form second recessed areas and at least one of second mesas or a first seal band area; and removing a second mask from the support plate.

Abstract: A gas conditioning apparatus comprising a substrate block comprising one or more fluid ports on an upper surface of the substrate block. The substrate block has a first length along a sidewall. The substrate block comprises an inlet port at a first end and an outlet port at a second end. A flow passage extends within the substrate block between the inlet port and the outlet port and is in fluidic communication with the one or more fluid ports. At least one heater strip is on the sidewall of the substrate block. The at least one heater strip extends between the first end and the second end and is to control an internal temperature within a zone of the substrate block. The zone has a second length that is less than or substantially equal to the first length.

Abstract: A patterning method includes etching a mask formed above a stack of two or more layers where the mask comprises a first patterned structure, a second patterned structure above the first patterned structure, where portions of the second patterned structure intersect the first patterned structure to form intersections and at least an opening. The mask includes a structure vertically between portions of the second patterned structure and the stack. The method includes etching a first layer of the stack through the opening and exposing a top surface of a second layer below the first layer, etching and removing the first patterned structure and the second patterned structure selectively to the first layer and the top surface of the second layer to form a planar mask comprising the first layer. The method further includes etching the second layer of the stack using the planar mask.