Patents Assigned to Lam Research
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Patent number: 12278125Abstract: Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.Type: GrantFiled: October 5, 2023Date of Patent: April 15, 2025Assignee: Lam Research CorporationInventors: Jengyi Yu, Samantha S. H. Tan, Mohammed Haroon Alvi, Richard Wise, Yang Pan, Richard Alan Gottscho, Adrien Lavoie, Sivananda Krishnan Kanakasabapathy, Timothy William Weidman, Qinghuang Lin, Jerome S. Hubacek
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Patent number: 12278112Abstract: A method for performing an etch process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, wherein each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state. The power level of the bias signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state. The power level of the source signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state.Type: GrantFiled: June 16, 2022Date of Patent: April 15, 2025Assignee: Lam Research CorporationInventors: Aniruddha Joi, Nikhil Dole, Merrett Wong, Eric Hudson, Jay Sheth
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Publication number: 20250118592Abstract: Semiconductor processing tools with wafer back-side processing capabilities are disclosed. Such tools may be configured to only contact wafers being processed through edge contact, as opposed to underside/planar contact. Such tools may also include wafer-centering features that may allow such wafers to be precisely centered with regard to a particular wafer processing station thereof.Type: ApplicationFiled: January 18, 2023Publication date: April 10, 2025Applicant: Lam Research CorporationInventors: Nick Ray Linebarger, Jr., Richard M. Blank, Daniel Boatright, Fayaz A. Shaikh, Eric Thomas Dixon, Michael John Janicki, Adriana Vintila, Xin Yin, Conor Charles Arcuri
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Patent number: 12272583Abstract: A system comprises an equipment front end module (EFEM), a vacuum transfer module (VTM), a plurality off quad station process modules (QSMs). The EFEM is configured to receive a plurality of wafers. The EFEM comprises an EFEM transfer robot. The vacuum transfer module (VTM) is configured to receive the plurality of wafers from the EFEM. The VTM comprises a VTM transfer robot. The plurality of quad station process modules (QSMs) is coupled to the VTM. The VTM transfer robot is configured Oto transfer wafers between the VTM and the plurality of QSMs. The EFEM transfer robot is configured to transfer wafers between the EFEM and the VTM.Type: GrantFiled: June 18, 2019Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Christopher W. Burkhart, Richard H. Gould, Candi Kristoffersen, Michael Nordin, Richard M. Blank, Hironobu Yasuumi
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Patent number: 12272608Abstract: Methods for reducing warpage of bowed semiconductor substrates, including providing a first substrate to a first station in a semiconductor processing chamber, providing a second substrate to a second station in the semiconductor processing chamber, concurrently depositing a first bow compensation layer of material on the backside of the first substrate at the first station and a first bow compensation layer of material on the backside of the second substrate at the second station, and depositing a second bow compensation layer of material on the backside of the first substrate, while the first substrate is at the first station and the second substrate is at the second station, and while not concurrently depositing material on the backside of the second substrate.Type: GrantFiled: December 10, 2020Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Yanhui Huang, Vignesh Chandrasekar
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Patent number: 12270103Abstract: Methods and apparatuses for depositing thin films using plasma-enhanced atomic layer deposition (PEALD) with ramping radio-frequency (RF) power are provided herein. Embodiments involve increasing the RF power setting of PEALD cycles after formation of initial screening layers at low RF power settings.Type: GrantFiled: November 5, 2020Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Jeremy David Fields, Frank Loren Pasquale
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Patent number: 12272571Abstract: Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.Type: GrantFiled: April 9, 2024Date of Patent: April 8, 2025Assignee: LAM RESEARCH CORPORATIONInventors: Dengliang Yang, Haoquan Fang, David Cheung, Gnanamani Amburose, Eunsuk Ko, Wei Yi Luo, Dan Zhang
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Patent number: 12272570Abstract: Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.Type: GrantFiled: April 9, 2024Date of Patent: April 8, 2025Assignee: LAM RESEARCH CORPORATIONInventors: Dengliang Yang, Haoquan Fang, David Cheung, Gnanamani Amburose, Eunsuk Ko, Wei Yi Luo, Dan Zhang
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Patent number: 12270748Abstract: An apparatus for measuring contamination on a critical surface of a part is provided. A vessel for mounting the part is provided. An inert gas source is in fluid connection with the vessel and adapted to provide an inert gas to the vessel. At least one diffuser receives the inert gas from the vessel, wherein the critical surface of the part is exposed to the inert gas when the part is mounted in the vessel. At least one analyzer is adapted to receive inert gas from the at least one diffuser and measures contaminants in the inert gas.Type: GrantFiled: September 5, 2019Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Amir A. Yasseri, Girish M. Hundi, John Michael Kerns, Duane Outka, John Daugherty, Cliff La Croix
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Patent number: 12274047Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.Type: GrantFiled: December 22, 2023Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Gorun Butail, Shruti Thombare, Ishtak Karim, Patrick Van Cleemput
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Patent number: 12272591Abstract: In an example, a showerhead pedestal assembly for a substrate processing chamber is provided. The showerhead pedestal assembly includes a faceplate. A platen is disposed within the faceplate and includes a heater element extending through at least one groove in the faceplate. The at least one groove is profiled to accept at least one portion of the heater element. A periphery of the platen is joined to an interior surface of the faceplate by a friction stir welded joint.Type: GrantFiled: March 12, 2020Date of Patent: April 8, 2025Assignee: Lam Research CorporationInventors: Nick Ray Linebarger, Jr., Prahalad Narasinghdas Agarwal, Ravikumar Sadashiv Patil, Damodar Rajaram Shanbhag
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Publication number: 20250112045Abstract: Dry development of resists can be useful, for example, to form a patterning mask in the context of high-resolution patterning. Dry development may be advantageously accomplished by a method of processing a semiconductor substrate including providing in a process chamber a photopatterned resist on a substrate layer on a semiconductor substrate, and dry developing the photopatterned resist by removing either an exposed portion or an unexposed portion of the resist by a dry development process comprising exposure to a chemical compound to form a resist mask. The resist may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film EUV resist.Type: ApplicationFiled: December 13, 2024Publication date: April 3, 2025Applicant: Lam Research CorporationInventors: Boris Volosskiy, Timothy William Weidman, Samantha SiamHwa Tan, Chenghao Wu, Kevin Li Gu
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Patent number: 12266505Abstract: A method for achieving uniformity in an etch rate is described. The method includes receiving a voltage signal from an output of a match, and determining a positive crossing and a negative crossing of the voltage signal for each cycle of the voltage signal. The negative crossing of each cycle is consecutive to the positive crossing of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the plurality of bins associated with the positive crossing and one or more of the plurality of bins associated with the negative crossing, the method includes adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate.Type: GrantFiled: February 8, 2021Date of Patent: April 1, 2025Assignee: Lam Research CorporationInventors: Alexei Marakhtanov, Felix Leib Kozakevich, Ranadeep Bhowmick, Bing Ji, John Holland
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Patent number: 12266542Abstract: A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.Type: GrantFiled: February 7, 2024Date of Patent: April 1, 2025Assignee: Lam Research CorpporationInventors: Wenbing Yang, Mohand Brouri, Samantha SiamHwa Tan, Shih-Ked Lee, Yiwen Fan, Wook Choi, Tamal Mukherjee, Ran Lin, Yang Pan
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Patent number: 12266588Abstract: A temperature-controlled pedestal includes a pedestal, a temperature sensor to sense N temperature in N zones, and N temperature control devices arranged in the N zones, respectively. A voltage source selectively supplies power to the N temperature control devices. A controller is configured to cause the voltage source to control a temperature in the N zones by a) determining a hottest one of the N zones based on the N temperatures; b) if the hottest one of the N zones is not already cooling, increasing cooling to the hottest one of the N zones using one of the N temperature control devices; c) decreasing cooling to the N zones when a temperature of the N zones is less than a first temperature setpoint; and d) repeating a) to c) until all of the N zones have a temperate less than or equal to the first temperature setpoint.Type: GrantFiled: July 9, 2020Date of Patent: April 1, 2025Assignee: LAM RESEARCH CORPORATIONInventors: Mrinal Kumar, Harisprasad Hegde, Vishwajith Nirebailur, Harish Neelam Reddy
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Patent number: 12261044Abstract: Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.Type: GrantFiled: February 23, 2021Date of Patent: March 25, 2025Assignees: Lam Research Corporation, International Business Machines CorporationInventors: Bhaskar Nagabhirava, Phillip Friddle, Ekimini Anuja De Silva, Jennifer Church, Dominik Metzler, Nelson Felix
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Patent number: 12261029Abstract: A direct drive system for providing RF power to a component of a substrate processing system includes a direct drive circuit including a switch and configured to supply RF power to the component. A switch protection module is configured to monitor a load current and a load voltage in a processing chamber, calculate load resistance based on the load current and the load voltage, compare the load resistance to a first predetermined load resistance, and adjust at least one of an RF power limit and an RF current limit of the direct drive circuit based on the comparison.Type: GrantFiled: June 10, 2021Date of Patent: March 25, 2025Assignee: Lam Research CorporationInventors: Maolin Long, Yuhou Wang, Michael John Martin, Alexander Miller Paterson
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Patent number: 12261018Abstract: A plenum for a dielectric window of a substrate processing system includes a first inlet port, a second inlet port, and a body. The body includes: a first recessed area configured to hold a first coil; a second recessed area configured to hold a second coil; a third recessed area configured to oppose a first area of the dielectric window, receive a first coolant from the first inlet port, and direct the first coolant across the first area to cool a first portion of the dielectric window; and a fourth recessed area configured to oppose a second area of the dielectric window, receive a second coolant from the second inlet port, and direct the second coolant across the second area to cool a second portion of the dielectric window.Type: GrantFiled: January 22, 2021Date of Patent: March 25, 2025Assignee: Lam Research CorporationInventor: Hanry Issavi
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Patent number: 12261081Abstract: Methods for selective inhibition control in semiconductor manufacturing are provided. An example method includes providing a substrate including a feature having one or more feature openings and a feature interior. A nucleation layer is formed on a surface of the feature interior. Based on a differential inhibition profile, a nonconformal bulk layer is selectively formed on a surface of the nucleation layer to leave a region of the nucleation layer covered, and a region of the nucleation layer uncovered by the nonconformal bulk layer. An inhibition layer is selectively formed on the covered and uncovered regions of the nucleation layer. Tungsten is deposited in the feature in accordance with the differential inhibition profile.Type: GrantFiled: February 13, 2020Date of Patent: March 25, 2025Assignee: Lam Research CorporationInventors: Tsung-Han Yang, Michael Bowes, Gang Liu, Anand Chandrashekar
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Patent number: D1069043Type: GrantFiled: December 17, 2021Date of Patent: April 1, 2025Assignee: Lam Research CorporationInventors: Danae Nicole Kay, Thomas Mark Pratt, Matthew Palmer Kwan