Patents Assigned to Lapis Semiconductor Co., Ltd.
  • Patent number: 10910331
    Abstract: A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 2, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 10901041
    Abstract: A semiconductor device includes: a first and a second receiving sections that receive control signals from outside; a control section that controls monitoring of an object based on the control signals; and a power supply section that supplies power to internal circuits of the semiconductor device, wherein, when the power supply section is in a halted state, and when the first receiving section receives an activation, the first receiving section generates an activation trigger that activates the power supply section based on the activation pulse signal extracted from the activation signal, and wherein the second receiving section receives a supply of power from the power supply section after the power supply section has been activated by the activation trigger, and receives the control signals that follows the activation signal, and sends the control signals to the control section.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 26, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Makoto Nagasue
  • Publication number: 20210019216
    Abstract: A signal processing circuit has: n+1 (n being an integer of 2 or greater) operation circuits, each of which is configured to execute a prescribed operation process on inputted data; a signal supply unit that is configured to receive n pieces of input data extracted from one input signal and receive test data inputted separately from the n pieces of input data, sequentially select one operation circuit among the n+1 operation circuits and supply the test data to the one selected operation circuit, and supply the n pieces of input data to n operation circuits other than the one operation circuit among the n+1 operation circuits; and an anomaly determination unit that is configured to determine whether an anomaly has occurred in the one operation circuit on the basis of an operation result of an operation on the test data by the one operation circuit.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 21, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Naohiro FUJII, Yuki IMATOH
  • Publication number: 20210012731
    Abstract: A display driver according to the present invention includes a withstand voltage protection part that precharges an output node of a polarity changeover switch circuit that switches a polarity of a drive signal supplied to a display device from an electric potential of a positive polarity (a first electric potential to a third electric potential) to an electric potential of a negative polarity (the third electric potential to a second electric potential) or vice versa to the third electric potential immediately before the polarity switching.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Kenichi SHIIBAYASHI
  • Patent number: 10892165
    Abstract: A semiconductor manufacturing device including: a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that is configured to output a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that is configured to derive a depth of the groove from the measurement value of the measuring section.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 12, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kiyohiko Toshikawa, Hiroyuki Baba
  • Patent number: 10892189
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 12, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Osamu Koike, Yutaka Kadogawa
  • Publication number: 20210004207
    Abstract: A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal.
    Type: Application
    Filed: June 29, 2020
    Publication date: January 7, 2021
    Applicants: LAPIS Semiconductor Co., Ltd., TAMAGAWA SEIKI Co., Ltd.
    Inventors: Masato YAMAZAKI, Hirofumi MARUYAMA
  • Patent number: 10880484
    Abstract: An imaging device and a horizontal direction detection method capable of detecting a horizontal angle of a camera with high accuracy in a simple configuration are provided. The imaging device includes an imaging unit configured to obtain image data by photographing a predetermined subject, an image rotation unit configured to cause a display image based on the image data to be rotated on a display plane step by step, a count unit configured to count the number of pixels of a specific color included in the display image in a scanning line direction within the display plane and obtain a count value for each of rotated display images, and a determination unit configured to determine a horizontal direction of a photographing angle of the imaging unit based on the count value for each of the rotated display images.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 29, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yuki Imatoh
  • Patent number: 10868152
    Abstract: A semiconductor device including a memory cell, the semiconductor device including: a floating gate provided at a semiconductor substrate with a first insulation film inbetween, and including a pointed portion having a pointed end at one end side; a spacer provided at the floating gate; a second insulation film provided between the floating gate and the spacer and that covers a side surface of the spacer at the one end side; and a control gate that contacts a side surface of the floating gate at the one end side via a third insulation film and that contacts the side surface of the spacer at the one end side via the second insulation film and the third insulation film.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akira Chiba
  • Patent number: 10867541
    Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20200388932
    Abstract: A semiconductor device includes a first antenna element, a second antenna element, and a semiconductor chip including a communication circuit that is connected to the first antenna element and the second antenna element. The first antenna element and the second antenna element are disposed on opposite surfaces of the semiconductor chip. The first antenna element or the second antenna element to which a ground potential is applied has a grid-like pattern.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroji Akahori
  • Patent number: 10861510
    Abstract: A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 8, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Nobukazu Murata
  • Patent number: 10847091
    Abstract: A display driver includes a data fetching unit that fetches first to Nth pixel data pieces corresponding to luminance levels of respective pixels and outputs the same at a timing of an edge of a clock signal, first to Nth amplifiers that amplify first to Nth gradation voltages corresponding to the first to Nth pixel data piece to obtain first to Nth driving voltages, and a bias voltage generation unit that generates and supplies bias voltages for setting current values of operation currents to the respective amplifiers. The bias voltage generation unit stores a first value and a second value of the bias voltage used for setting the current value to a higher value and a lower value, and generates a bias voltage having the first value during a period from the timing of the edge of the clock signal, and switches the voltage value to the second value thereafter.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 24, 2020
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroki Aizawa
  • Patent number: 10845838
    Abstract: A reference voltage generation circuit including: a first diode including a first conductive area; a second diode including a second conductive area that is larger than the first conductive area; a generation section configured to generate a reference voltage using a voltage based on the first diode and a voltage based on the second diode; and a first capacitor connected between a node of dividing resistors and an output of the generation section, the dividing resistors being connected between the output of the generation section and the second diode.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 24, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Tanikawa
  • Patent number: 10838442
    Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: November 17, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shigeru Nagatomo
  • Publication number: 20200356132
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 10826289
    Abstract: The disclosure provides a wireless power supply device, which includes: a power transmission coil; a first driving unit that alternatively performs an operation of transmitting a first driving current to one end of the power transmission coil and an operation of drawing a second driving current away from one end of the power transmission coil; a second driving unit that alternatively performs an operation of transmitting the second driving current to the other end of the power transmission coil and an operation of drawing the first driving current away from the other end of the power transmission coil; a current detection unit that detects amounts of the transmitted first and second driving current to generate a first signal, and detects an amount of the drawn second driving current to generate a second signal; and a control unit that determines an operation state based on the first and second signal.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 3, 2020
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Takashi Taya
  • Patent number: 10818376
    Abstract: A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: October 27, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiharu Okada
  • Patent number: 10818218
    Abstract: A display driver includes gradation voltage generation circuits; n DA converters configured to select and output a gradation voltage corresponding to pixel data, out of the gradation voltages generated by the gradation voltage generation circuit; n amplifiers configured to independently amplify n gradation voltages outputted from the DA converters, to generate n amplified gradation voltages; and a selector configured to output the n amplified gradation voltages from n output terminals, respectively, in a normal mode. In a power save mode, one of the gradation voltage generation circuits generates a gradation voltage, and the other gradation voltage generation circuits stop. In the power save mode, the selector outputs selected one of k amplified gradation voltages from k output terminals, and opens an output terminal of each amplifier, except for an amplifier for generating the one amplified gradation voltage, out of the k amplifiers configured to generate the k amplified gradation voltages.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 27, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Koya Sugihara, Atsushi Hirama
  • Patent number: 10817008
    Abstract: A semiconductor device includes a circuit-to-be-adjusted in which an output characteristic thereof can be adjusted by a fuse that is controlled based on a fuse signal. The semiconductor device includes a control circuit using, as a power source, an internal power source that has a converted voltage obtained by converting a voltage of an external power source, the control circuit being configured to generate control signals A, B based on an inputted test signal, the control signals being able to adjust the circuit-to-be-adjusted in place of the fuse signal. The semiconductor device includes a selector circuit that selects the fuse signal before the internal power source reaches a stable state after the external power source is turned on, and selects the control signal CS after the internal power source has reached a stable state.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 27, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takuya Matsumoto